BH62UV1601
LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
VDR≧1.0V
VCC
tCDR
VCC
tR
VCC
CE2≦0.2V
CE2
VIL
VIL
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
VCC / 0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
MUST BE
STEADY
MUST BE
STEADY
Input and Output Timing
Reference Level
0.5Vcc
tCLZ1, tCLZ2, tOLZ, tCHZ1
,
MAY CHANGE
WILL BE CHANGE
FROM “H” TO “L”
CL = 5pF+1TTL
CL = 30pF+1TTL
tCHZ2, tOHZ, tWHZ, tOW
Output Load
FROM “H” TO “L”
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
VCC
GND
CHANGE :
1 TTL
90%
90%
STATE UNKNOW
Output
10%
10%
(1)
→
←
→
←
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
CL
DOES NOT
APPLY
Rise Time:
Fall Time:
1V/ns
1V/ns
1. Including jig and scope capacitance.
AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
CYCLE TIME : 55ns CYCLE TIME : 70ns
PARANETER
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
(VCC = 3.0V)
(VCC = 1.8V)
UNITS
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tRC
55
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
30
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
30
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQX
tAA
Address Access Time
--
--
tE1LQV
tE2HQV
tGLQV
tE1LQX
tE2HQX
tGLQX
tE1HQZ
tE2LQZ
tGHQZ
tAVQX
tACS1
tACS2
tOE
Chip Select Access Time
(CE1)
(CE2)
--
--
Chip Select Access Time
--
--
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
--
--
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
tOH
(CE1) 10
(CE2) 10
5
10
10
10
--
--
--
--
--
(CE1)
(CE2)
--
--
25
25
25
--
35
35
30
--
--
--
--
10
10
Revision
Oct.,
1.2
R0201-BH62UV1601
4
2008
BSI [ BRILLIANCE SEMICONDUCTOR ]
