BSI
BH62UV8000
WRITE CYCLE 2 (1,6)
tWC
ADDRESS
(11)
tCW
(5)
(5)
CE1
CE2
(11)
(2)
tCW
(3)
tAW
tWR2
tWP
WE
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of the signal
that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BH62UV8000
Revision 1.0
Jul. 2005
7