t1
R/C
t12
t2
t3
t5
t4
BUSY
MODE
t6
Convert
t7
Acquire
t8
Convert
Acquire
Hi-Z State
Data Valid
t10
HI Z State
DATA BUS
Data Valid
t9
FIGURE 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low).
The nominal input impedance of 3.125kΩ results from the
combination of the internal resistor network shown on page 3
of this data sheet and the external 50Ω resistor. The input
resistor divider network provides inherent over-voltage pro-
tection guaranteed to at least ±25V. The 50Ω, 1% resistor
does not compromise the accuracy or drift of the converter. It
has little influence relative to the internal resistors, and tighter
tolerances are not required.
READING DATA
The ADS7831 outputs full parallel data in Binary Two’s
Complement data output format. The parallel output will be
active when R/C (pin 23) is HIGH, CS (pin 24) is LOW, and
no conversion is in progress. Any other combination will tri-
state the parallel output. Valid conversion data can be read in
a full parallel, 12-bit word on D11-D0 (pins 6-13 and 15-18).
Refer to Table II for ideal output codes.
Note: The values shown for the internal resistors are for
reference only. The exact values can vary by ±30%. This is
true of all resistors internal to the ADS7831. Each resistive
divider is trimmed so that the proper division is achieved.
After the conversion is completed and the output registers
have been updated, BUSY (pin 25) will go HIGH. Valid data
from the most recent conversion will be available on
D11-D0 (pins 6-13 and 15-18). BUSY going HIGH can be
used to latch the data. Refer to Table III and Figures 2 and 3.
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
Note: For best performance, the external data bus connected
to D11-D0 should not be active during a conversion. The
switching noise of the external asynchronous data signals
can cause digital feed through degrading the converter’s
performance.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
ns
t1
t2
Convert Pulse Width
40
Data Valid Delay
After Start of Conversion
1310
75
1460
125
ns
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 2.
t3
BUSY Delay
From Start of Conversion
ns
t4
t5
BUSY LOW
1300
90
1440
ns
ns
BUSY Delay After
End of Conversion
ANALOG INPUT
t6
Aperture Delay
Conversion Time
Acquisition Time
Throughput Time
Bus Relinquish Time
20
1285
200
1485
55
ns
ns
ns
ns
ns
ns
The ADS7831 has a ±2.5V input range. Figures 4a and 4b
show the necessary circuit connections for the ADS7831
with and without external trim. Offset and full scale error(1)
specifications are tested and guaranteed with the 50Ω resis-
tor shown in Figure 4b. This external resistor makes it
possible to trim the offset ±12mV using R1 and P1 as shown
in Figure 4a. This resistor may be left out if the offset and
gain errors will be corrected in software or if they are
negligible in regards to the particular application. See the
Calibration section of the data sheet for details.
t7
1400
250
1650
83
t8
t7 & t8
t9
10
20
t10
BUSY Delay
After Data Valid
65
100
t11
t12
t13
R/C to CS
Setup Time
10
1660
10
ns
ns
ns
Time Between
Conversions
Bus Access Time
30
62
TABLE III. Timing Specifications (TMIN to TMAX).
®
ADS7831
8
BB [ BURR-BROWN CORPORATION ]
