PIN ASSIGNMENTS
DIGITAL
I/O
PIN #
NAME
DESCRIPTION
1
2
3
VIN
AGND1
REF
Analog Input. Connect via 50Ω to analog input. Full-scale input range is ±10V.
Analog Ground. Used internally as ground reference point. Minimal current flow.
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system
reference. In both cases, decouple to ground with a 0.1µF ceramic capacitor.
Reference Buffer Output. 10µF tantalum capacitor to ground. Nominally +2V.
Analog Ground.
4
5
6
CAP
AGND2
D11 (MSB)
O
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
7
8
9
D10
D9
D8
D7
D6
D5
D4
DGND
D3
D2
O
O
O
O
O
O
O
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Digital Ground.
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
10
11
12
13
14
15
16
17
18
O
O
O
O
D1
D0 (LSB)
19
20
21
22
23
Not internally connected.
+VANA
+VDIG
DGND
R/C
Analog Positive Supply Input. Nominally +5V. Connect directly to pins 21, 27 and 28.
Digital Supply Input. Nominally +5V. Connect directly to pins 20, 27 and 28.
Digital ground.
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and
starts a conversion. With CS LOW and no conversion in progress, a rising edge on R/C enables the output
data bits.
I
24
25
CS
I
Chip Select. With R/C LOW, a falling edge on CS will initiate a conversion. With
R/C HIGH and no conversion in progress, a falling edge on CS will enable the output data bits.
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the
data is latched into the output register. With CS LOW and R/C HIGH, output data will be valid when BUSY
rises, so that the rising edge can be used to latch the data.
BUSY
O
26
–VANA
Analog Negative Supply Input. Nominally –5V. Decouple to ground with 0.1µF ceramic and 10µF tantulum
capacitors.
27
28
+VDIG
+VANA
Digital Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 28.
Analog Positive Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 27, and decouple to ground
with 0.1µF ceramic and 10µF tantulum capacitors.
PIN CONFIGURATION
VIN
AGND1
REF
1
2
3
4
5
6
7
8
9
28 +VANA
27 +VDIG
26 –VANA
25 BUSY
24 CS
CAP
AGND2
D11 (MSB)
D10
23 R/C
22 DGND
21 +VDIG
20 +VANA
19 NC(1)
18 D0 (LSB)
17 D1
ADS7810
D9
D8
D7 10
D6 11
D5 12
D4 13
16 D2
DGND 14
15 D3
NOTE: (1) Not Internally Connected.
®
ADS7810
4
BB [ BURR-BROWN CORPORATION ]
