To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. Note that
the parallel output will be active whenever R/C is HIGH and
no conversion is in progress. See the Reading Data section
and refer to Table I for control line functions for ‘read’ and
‘convert’ modes.
The nominal input impedance of 3.125kΩ results from the
combination of the internal resistor network shown on the
front page of the product data sheet and external 50Ω
resistor. The input resistor divider network provides inherent
overvoltage protection guaranteed to at least ±25V. The
50Ω, 1% resistor does not compromise the accuracy or drift
of the converter. It has little influence relative to the internal
resistors, and tighter tolerances are not required.
READING DATA
Note: The values shown for the internal resistors are for
reference only. The exact values can vary by ±30%. This is
true of all resistors internal to the ADS7810. Each resistive
divider is trimmed so that the proper division is achieved.
The ADS7810 outputs full parallel data in Binary Two’s
Complement data format. The parallel output will be active
when R/C (pin 23) is HIGH, CS (pin 24) is LOW, and no
conversion is in progress. Any other combination will tri-
state the parallel output. Valid conversion data can be read
in a full parallel, 12-bit word on D11-D0 (pins 6-13 and 15-
18). Refer to Table II for ideal output codes.
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
After the conversion is completed and the output registers
have been updated, BUSY (pin 25) will go HIGH. Valid data
from the most recent conversion will be available on
D11-D0 (pins 6-13 and 15-18). BUSY going HIGH can be
used to latch the data. Refer to Table III and Figures 2
and 3.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
ns
t1
t2
Convert Pulse Width
40
Data Valid Delay
After R/C LOW
955
70
1095
125
ns
t3
BUSY Delay
ns
Note: For the best performance, the external data bus con-
nected to D11-D0 should not be active during a conversion.
The switching noise of the external asynchronous data
signals can cause digital feedthrough degrading the
converter’s performance.
From R/C LOW
t4
t5
BUSY LOW
950
90
1080
ns
ns
BUSY Delay After
End of Conversion
t6
Aperture Delay
Conversion Time
Acquisition Time
Throughput Time
Bus Relinquish Time
20
910
200
1110
50
ns
ns
ns
ns
ns
ns
t7
1020
230
1250
83
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 2.
t8
t7 & t8
t9
10
20
t10
BUSY Delay
After Data Valid
65
120
INPUT RANGES
t11
t12
t13
R/C to CS
Setup Time
10
1250
10
ns
ns
ns
The ADS7810 offers a standard ±10V input range. Figures
4a and 4b show the necessary circuit connections for the
ADS7810 with and without external trim. Offset and full
scale error(1) specifications are tested and guaranteed with
the 50Ω resistor shown in Figure 4b. This external resistor
makes it possible to trim the offset ±50mV using a trim pot
or trim DAC. This resistor may be left out if the offset and
gain errors will be corrected in software or if they are
negligible in regards to the particular application. See the
Calibration section of the data sheet for details.
Time Between
Conversions
Bus Access Time
25
62
TABLE III. Timing Specifications (TMIN to TMAX).
®
ADS7810
8
BB [ BURR-BROWN CORPORATION ]
