ADS5240
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SBAS326C–JUNE 2004–REVISED DECEMBER 2004
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 6pF. IO refers to the current setting for the LVDS buffer. RLOAD is
the differential load resistance between the LVDS pair. CLOAD is the effective single-ended load capacitance between each of
the LVDS pins and ground. CLOAD includes the receiver input parasitics as well as the routing parasitics. Measurements are
done with a transmission line of 100Ω characteristic impedance between the device and the load. All LVDS specifications are
characterized, but not tested at production.
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
(1)
DC SPECIFICATIONS
Output Voltage High, OUTP or OUTN
RLOAD = 100Ω± 1%
See LVDS Timing Diagram, Page 7
1375 1500
mV
VOH
VOL Output Voltage Low, OUTP or OUTN
|VOD Output Differential Voltage, |OUTP - OUTN|
VOS Output Offset Voltage(2)
RLOAD = 100Ω± 1%
RLOAD = 100Ω± 1%
900 1025
300 350
mV
mV
mV
|
400
RLOAD = 100Ω± 1%
1100 1200 1300
See LVDS Timing Diagram, Page 7
CO Output Capacitance(3)
VCM = 1.5V
4
pF
|∆VOD
|
Change in |VOD| Between 0 and 1
RLOAD = 100Ω± 1%
25
25
40
12
mV
mV
mA
mA
∆VOS Change Between 0 and 1
ISOUT Output Short-Circuit Current
ISOUTNP Output Current
RLOAD = 100Ω± 1%
Drivers Shorted to Ground
Drivers Shorted Together
DRIVER AC SPECIFICATIONS
Clock LVDS Clock Duty Cycle
Minimum Data Setup Time(4)(5)
Minimum Data Hold Time(4)(5)
6 × ADCLK (LCLKP, LCLKN)
45
50
55
%
ps
ps
ps
ps
ps
ps
650
650
400
250
200
150
tRISE/tFALL VOD Rise Time or VOD Fall Time
IO = 2.5mA
IO = 3.5mA
IO = 4.5mA
IO = 6mA
(1) The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
(2) VOS refers to the common-mode of OUTP and OUTN.
(3) Output capacitance inside the device, from either OUTP or OUTN to ground.
(4) Refer to the LVDS application note (SBAA118) for a description of data setup and hold times.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margins.
SWITCHING CHARACTERISTICS
TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted.
ADS5240
PARAMETER
SWITCHING SPECIFICATIONS
tSAMPLE
CONDITIONS
MIN
TYP
MAX
UNITS
25
50
ns
ns
tD(A) Aperture Delay
3.1
1
Aperture Jitter (uncertainty)
tD(pipeline) Latency
tPROP Propagation Delay
ps rms
Cycles
ns
6.5
5
6
BB [ BURR-BROWN CORPORATION ]
