ADS5240
www.ti.com
SBAS326C–JUNE 2004–REVISED DECEMBER 2004
SERIAL INTERFACE REGISTERS
ADDRESS
DATA
DESCRIPTION
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
LVDS BUFFERS (register 0)
Normal ADC Output
0
0
1
1
0
1
0
1
(default after reset)
Deskew Pattern
Patterns Get Reversed in MSB
First Mode of LVDS
Sync Pattern
Custom Pattern
0
0
1
1
0
1
0
1
Output Current in LVDS = 3.5mA
Output Current in LVDS = 2.5mA
Output Current in LVDS = 4.5mA
Output Current in LVDS = 6.0mA
LSB/MSB MODE (register 1)
Default LVDS Clock Output Current
2X LVDS Clock Output Current
LSB First Mode
(default after reset)
0
0
0
1
0
0
0
0
X
X
0
1
X
X
X
X
0
1
IOUT = 3.5mA
IOUT = 7.0mA
X
X
(default after reset)
MSB First Mode
0
0
0
0
1
1
0
1
POWER-DOWN ADC CHANNELS
(register 2)
0
0
1
0
0
X
1
D2: Power-Down for Channel 2
D0: Power-Down for Channel 1
Logic 1 = Channel Powered
Down
X
POWER-DOWN ADC CHANNELS
(register 3)
1
0
0
X
1
0
0
D3: Power-Down for Channel 4
D1: Power-Down for Channel 3
CUSTOM PATTERN (registers 4-6)
Bits for Custom Pattern
Logic 1 = Channel Powered
Down
X
D3
X
D2
X
D1
X
D0
X
See Test Patterns
0
0
0
1
1
1
0
0
1
0
1
0
X
X
X
X
X
X
X
X
TEST PATTERNS(1)
Deskew
Sync
101010101010
000000111111
Custom
Any 12-bit pattern that is defined in the custom pattern registers 4 to 6. The output comes out in the following
order:
D0(4) D1(4) D2(4) D3(4) D0(5) D1(5) D2(5) D3(5) D0(6) D1(6) D2(6) D3(6)
where, for example, D0(4) refers to the D0 bit of register 4, etc.
(1) Default is LSB first. If MSB first is selected, the above patterns will be reversed.
9
BB [ BURR-BROWN CORPORATION ]
