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ADS1271IPW 参数 Datasheet PDF下载

ADS1271IPW图片预览
型号: ADS1271IPW
PDF下载: 下载PDF文件 查看货源
内容描述: 24位高带宽模拟数字转换器 [24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER]
分类和应用: 转换器
文件页数/大小: 29 页 / 378 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ꢎꢒ ꢖꢗ ꢀ ꢘ ꢗ  
www.ti.com  
SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004  
ELECTRICAL CHARACTERISTICS (continued)  
All specifications at T = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, f  
= 27MHz, and V = +2.5V, unless otherwise noted.  
REF  
A
CLK  
ADS1271  
TYP  
PARAMETER  
Voltage Reference Inputs  
Reference input Voltage (V  
TEST CONDITIONS  
MIN  
MAX  
UNITS  
)
V
= VREFP – VREFN  
0.5  
AGND − 0.1  
VREFN + 0.5  
2.5  
2.65  
VREFP − 0.5  
AVDD + 0.1  
V
V
REF  
REF  
Negative reference input (VREFN)  
Positive reference input (VREFP)  
V
High-Speed mode  
4.2  
4.2  
8.4  
kΩ  
kΩ  
kΩ  
Reference Input  
impedance  
High-Resolution mode  
Low-Power mode  
Digital Input/Output  
V
V
V
V
0.7 DVDD  
DGND  
DVDD  
0.3 DVDD  
DVDD  
0.2 DVDD  
10  
V
V
IH  
IL  
I
I
= 5mA  
0.8 DVDD  
DGND  
V
OH  
OH  
= 5mA  
V
OL  
OL  
(4)  
Input leakage  
0 < V  
IN DIGITAL  
< DVDD  
µA  
Master clock rate (f  
)
1
27  
MHz  
MHz  
MHz  
MHz  
MHz  
CLK  
SPI format  
24 f  
64 f  
f
CLK  
DATA  
DATA  
DATA  
DATA  
High-Speed mode  
High-Resolution mode  
Low-Power mode  
64 f  
128 f  
64 f  
Serial clock rate  
DATA  
DATA  
DATA  
(5)  
(f )  
SCLK  
128 f  
64 f  
Frame-Sync format  
Power Supply  
AVDD  
4.75  
1.65  
5
5.25  
3.6  
25  
25  
9.5  
70  
10  
6
V
DVDD  
V
High-Speed mode  
High-Resolution mode  
Low-Power mode  
17  
17  
6.3  
1
mA  
mA  
mA  
µA  
AVDD current  
T 105°C  
T 85°C  
Power-Down mode  
1
µA  
High-Speed mode  
High-Resolution mode  
Low-Power mode  
3.5  
2.5  
1.8  
1
mA  
mA  
mA  
µA  
5
3.5  
70  
20  
136  
134  
54  
DVDD current  
T 105°C, DVDD = 3.3V  
T 85°C, DVDD = 3.3V  
Power-Down mode  
1
µA  
High-Speed mode  
High-Resolution mode  
Low-Power mode  
92  
90  
35  
mW  
mW  
mW  
Power dissipation  
Temperature Range  
Specified  
−40  
−40  
−60  
+105  
+105  
+150  
_C  
_C  
_C  
Operating  
Storage  
(1)  
(2)  
(3)  
(4)  
(5)  
FSR = full-scale range = 2V  
.
REF  
Minimum SNR is ensured by the limit of the DC noise specification.  
THD includes the first nine harmonics of the input signals.  
MODE and FORMAT pins excluded.  
See the text for more details on SCLK.  
4