SPECIFICATIONS
All specifications at TMIN to TMAX, VD = VS = +5V, CLK = 9.6MHz, PGA = 1, and VREF = 4.096, unless otherwise specified.
ADS1250U
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Input Voltage Range(1)
Programmable Gain Amplifier
Input Impedance (differential)
Input Capacitance
G = Gain
AGND
1
±VREF/G
V
8
G = Gain
G = Gain
At +25°C
104/G
6 • G
5
kΩ
pF
pA
nA
Input Leakage
50
1
At TMIN to TMAX
DYNAMIC CHARACTERISTICS
Data Rate
Bandwidth
25
kHz
kHz
3dB
5.4
Serial Clock (SCLK)
System Clock Input (CLK)
9.6
9.6
MHz
MHz
ACCURACY
Integral Linearity Error(2)
THD
Noise
±0.0012
97
2.8
±0.0020
% of FSR
1kHz Input; 0.1dB below FS
dB
ppm of FSR, rms
Bits
3.8
Resolution
20
No Missing Codes
Common-Mode Rejection(3)
Gain Error
Offset Error
Gain Sensitivity to VREF
Power Supply Rejection Ratio
20
105
Bits
dB
% of FSR
ppm of FSR
at DC
90
60
1
±200
±100
1:1
78
VREF = 4.096V ±0.1V
dB
PERFORMANCE OVER TEMPERATURE
Offset Drift
Gain Drift
0.25
5.0
ppm/°C
ppm/°C
VOLTAGE REFERENCE
VREF
Load Current
3.996V
4.096
125
4.196
V
µA
DIGITAL INPUT/OUTPUT
Logic Family
Logic Level: VIH
VIL
CMOS
+4.0
–0.3
+4.5
+VD + 0.3
+0.8
V
V
V
V
VOH
VOL
IOH = –500µA
IOL = 500µA
0.4
Data Format
Binary Two’s Complement
POWER SUPPLY REQUIREMENTS
Operation
Quiescent Current, Analog
Quiescent Current, Digital
Operating Power
+4.75
+5
14
1
+5.25
100
VDC
mA
mA
V = +5VDC
V = +5VDC
75
mW
TEMPERATURE RANGE
Operating
Storage
–40
–60
+85
+100
°C
°C
NOTES: (1) In order to achieve the converter’s full-scale range, the input must be fully differential. If the input is single-ended (+VIN or –VIN is fixed), then the
full-scale range is one-half that of the differential range. (2) Applies to full-differential signals. (3) The common-mode rejection test is performed with a 100mV
differential input.
®
ADS1250
2
BB [ BURR-BROWN CORPORATION ]
