DELTA-SIGMA MODULATOR
Reference voltages higher than 4.096V will increase the
full-scale range, while the absolute internal circuit noise of
the converter remains the same. This will decrease the noise
in terms of ppm of full scale. However, using a higher
reference voltage will also degrade linearity. Therefore, the
use of a higher reference voltage is not recommended.
The modulator clock is generated by dividing the system
clock by 6. With a nominal system clock frequency of
9.6MHz, the modulator clock frequency is 1.6MHz
(9.6MHz / 6). The output from the modulator is oversampled
64 times by the digital filter. Therefore, with 1.6MHz
modulator clock (derived from a 9.6MHz system clock), the
data output rate is 25kHz (1.6MHz / 64). The data output
rate scales directly with the system clock frequency, as
shown in Table II.
Reference voltages lower than 4.096V will decrease the full-
scale range, while the absolute internal circuit noise at the
converter remains the same. This will increase the noise in
terms of ppm of full scale. However, using a lower reference
voltage will not degrade linearity. Therefore, the use of a
lower reference voltage will reduce the effective resolution.
CLK (MHz)
DATA OUTPUT RATE (Hz)
9.600000
7.372800(1)
6.144000(1)
6.000000(1)
4.915200(1)
3.686400(1)
3.072000(1)
2.457600(1)
1.843200(1)
0.921600
0.460800
0.384000
0.192000
0.038400
0.023040
0.019200
0.011520
0.009600
0.007680
0.006400
0.005760
0.004800
0.003840
25,000
19,200
16,000
15,625
12,800
9,600
8,000
6,400
4,800
2,400
1,200
1,000
500
DIGITAL FILTER
The digital filter is a sinc5 and is described by the following
transfer function:
5
π • f • 64
sin
fMOD
H(f) =
π • f
64 •sin
fMOD
or
100
60
5
1– z–64
50
H(z) =
30
64 • 1– z–1
25
(
)
20
16.67
15
The digital filter of the ADS1250 computes the digital result
based on the most recent outputs from the delta-sigma
modulator. At the most basic level, the digital filter can be
thought of as simply averaging the modulator results in a
weighted form and presenting this average as the digital
result. The digital result is calculated from the digital filter
every 64 modulator clock cycles, or 6 • 64 = 384 system
clock cycles (refer to the Delta-Sigma Modulator section).
However, if there is a significant change in the analog input,
five full conversions are needed for the digital filter to settle.
If the analog input change occurs asynchronously to the
DRDY pulse, six conversions are needed for the conversion
to fully settle. Furthermore, the group delay is only 2.5
conversions due to the digital filter's linear phase response.
12.50
10
NOTE: (1) Standard Clock Oscillator.
TABLE II. CLK Rate versus Data Output Rate.
REFERENCE INPUT
Unlike the analog input, the reference input impedance has no
dependency on the PGA gain setting.
Reference input takes an average current of 125µA with a
9.6MHz system clock. This current will be proportional to
the system clock. A buffered reference is needed for
ADS1250. The recommended reference circuit is shown in
Figure 2.
+5V
+5V
0.10µF
7
4.99kΩ
2
To VREF
Pin 5 of
the ADS1250
6
OPA350
10kΩ
3
1
+
10µF
0.1µF
+
10µF
0.10µF
4
LM404-4.1
FIGURE 2. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the ADS1250.
®
9
ADS1250
BB [ BURR-BROWN CORPORATION ]
