ELECTRICAL CHARACTERISTICS
All specifications –40°C to +85°C, AVDD = 5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = 2.5V, unless otherwise specified.
ADS1244
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Voltage Range
Absolute Input Range
Differential Input Impedance
AINP – AINN
AINP, AINN with Respect to GND
fCLK = 2.4576MHz
±2VREF
V
V
MΩ
GND – 0.1
AVDD + 0.1
5
SYSTEM PERFORMANCE
Resolution
Data Rate
Integral Nonlinearity (INL)
Offset Error
No Missing Codes
fCLK = 2.4576MHz
Differential Input Signal, End Point Fit
24
Bits
15
±0.0002
1
sps(1)
±0.0008
10
% FSR(2)
ppm of FSR
Offset Error Drift(3)
Gain Error
Gain Error Drift(3)
Common-Mode Rejection
0.01
0.005
0.5
ppm of FSR/°C
0.02
%
ppm/°C
dB
dB
dB
dB
at DC
90
100
100
60
130
fCM(4) = 50 ± 1Hz, fCLK = 2.4576MHz
f
CM = 60 ± 1Hz, fCLK = 2.4576MHz
fSIG(5) = 50 ± 1Hz, fCLK = 2.4576MHz
Normal-Mode Rejection
fSIG = 60 ± 1Hz, fCLK = 2.4576MHz
70
dB
Input Referred Noise
1
ppm of FSR, rms
Analog Power-Supply Rejection
Digital Power-Supply Rejection
at DC, ∆AVDD = 5%
at DC, ∆DVDD = 5%
105
100
dB
dB
VOLTAGE REFERENCE INPUT
Reference Input Voltage (VREF
)
VREF ≡ VREFP – VREFN
0.5
2.5
1
AVDD(6)
VREFP – 0.5
AVDD + 0.1
V
V
V
Negative Reference Input (VREFN)
Positive Reference Input (VREFP)
Voltage Reference Impedance
GND – 0.1
VREFN + 0.5
fCLK = 2.4576MHz
MΩ
DIGITAL INPUT/OUTPUT
Logic Levels
VIH (CLK, SCLK)
VIL (CLK, SCLK)
2.1
GND
2.6
5.25
0.9
V
V
V
VOH
VOL
(
DRDY/DOUT
)
)
IOH = 1mA
IOL = 1mA
0 < (CLK, SCLK) < DVDD
(
DRDY/DOUT
0.4
±10
6
V
Input Leakage (CLK, SCLK)
CLK Frequency (fCLK
CLK Duty Cycle
µA
MHz
%
)
30
70
POWER SUPPLY
AVDD
DVDD
2.5
1.8
5.25
3.6
1
V
V
AVDD Current
Sleep Mode
AVDD = 3V
AVDD = 5V
0.1
85
90
0.1
1.3
4.5
270
µA
µA
µA
µA
µA
µA
µW
150
DVDD Current
Sleep Mode, CLK Stopped
Sleep Mode, 2.4576MHz CLK Running
DVDD = 3V
5
10
Total Power Dissipation
AVDD = DVDD = 3V
NOTES: (1) sps = Samples Per Second. (2) FSR = Full-Scale Range = 4VREF. (3) Recalibration can reduce these errors to the level of the noise. (4) fCM is the frequency
of the common-mode input. (5) fSIG is the frequency of the input signal. (6) It will not be possible to reach the digital output full-scale code when VREF > AVDD/2.
ADS1244
3
SBAS273
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