To help see the response at lower frequencies, Figure 7
illustrates the response out to 180Hz. Notice that both 50Hz
and 60Hz signals are rejected. This feature is very useful for
eliminating power line cycle interference during measure-
ments. Figure 8 shows the ADS1244’s response around
these frequencies.
The ADS1244’s data rate and frequency response scale
directly with CLK frequency. For example, if fCLK increases
from 2.4576MHz to 4.9152MHz, the data rate increases from
15sps to 30sps while the notches in the response at 50Hz
and 60Hz move out to 100Hz and 120Hz.
SETTLING TIME
FREQUENCY RESPONSE TO 180Hz
The ADS1244 has single-cycle settling. That is, the output
data is fully settled after a single conversion—there is no
need to wait for additional conversions before retrieving the
data when there is a change on the analog inputs.
fCLK = 2.4576MHz
0
–20
–40
In order to realize single-cycle settling, synchronize changes
on the analog inputs to the conversion beginning, which is
indicated by the falling edge of DRDY/DOUT. For example,
when using a multiplexer in front of the ADS1244, change the
multiplexer’s inputs when DRDY/DOUT goes LOW. Increas-
ing the time between the conversion beginning and the
change on the analog inputs (tDELAY) will result in a settling
error in the conversion data, as shown in Figure 9. The
settling error versus delay time is shown in Figure 10. If the
input change is delayed to the point where the settling error
is too high, simply ignore the first data result and wait for the
second conversion which will be fully-settled.
–60
–80
–100
–120
–140
–160
–180
Frequency (Hz)
FIGURE 7. Frequency Response to 180Hz.
FREQUENCY RESPONSE NEAR 50Hz AND 60Hz
SETTLING ERROR vs DELAY TIME
f
CLK = 2.4576MHz
f
CLK = 2.4576MHz
–40
–50
10.000000
1.000000
0.100000
0.010000
0.001000
0.000100
0.000010
0.000001
–60
–70
–80
–90
–100
–110
–120
45
50
55
60
65
0
2
4
6
8
10
12
14
16
Frequency (Hz)
Delay Time, tDELAY (ms)
FIGURE 8. Frequency Response Near 50Hz and 60Hz.
FIGURE 10. Settling Error vs Delay Time.
Begin New Conversion,
Complete Previous Conversion
Previous Conversion Data
New Conversion Complete
DRDY/DOUT
tDELAY
VIN
FIGURE 9. Analog Input Change Timing.
ADS1244
9
SBAS273
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