Minimize the overshoot and undershoot on CLK for the best
analog performance. A small resistor in series with CLK (10Ω
to 100Ω) can often help. CLK can be generated from a number
of sources including stand-alone crystal oscillators and
microcontrollers. The MSP430, an ultra low power
microcontroller, is especially well suited for this task. Using the
MSP430’s FLL clock generator available on the 4xx family, it’s
easy to produce a 2.4576MHz clock from a 32.768kHz crystal.
VOLTAGE REFERENCE INPUTS (VREFP, VREFN)
The voltage reference used by the modulator is generated
from the voltage difference between VREFP and VREFN:
VREF = VREFP – VREFN. The reference inputs use a structure
similar to that of the analog inputs. A simplified diagram of the
circuitry on the reference inputs is shown in Figure 5. The
switches and capacitors can be modeled with an effective
tSAMPLE
/25pF
impedance =
= 1MΩ for fCLK = 2.4576MHz.
2
DATA READY/DATA OUTPUT (
)
DRDY/DOUT
VREFP
VREFN
This digital output pin serves two purposes. It indicates when
new data is ready by going LOW. Afterwards, on the first rising
edge of SCLK, the DRDY/DOUT pin changes function and
begins outputting the conversion data, MSB first. Data is
shifted out on each subsequent SCLK rising edge. After all 24
bits have been retrieved, the pin can be forced HIGH with an
additional SCLK. It will then stay HIGH until new data is ready.
This is useful when polling on the status of DRDY/DOUT to
determine when to begin data retrieval.
AVDD
AVDD
ESD
S1
S1
Protection
25pF
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising edge.
As with CLK, this input may be driven with 5V logic regard-
less of the DVDD or AVDD voltage. There is hysteresis built
into this input, but care should still be taken to ensure a clean
signal. Glitches or slow rising signals can cause unwanted
additional shifting. For this reason, it is best to make sure the
rise-and-fall times of SCLK are less than 50ns.
S2
FIGURE 5. Simplified Reference Input Circuitry.
ESD diodes protect the reference inputs. To prevent
these diodes from turning on, make sure the voltages on
the reference pins do not go below GND by more than
100mV, and likewise do not exceed AVDD by 100mV:
GND – 100mV < (VREFP, VREFN) < AVDD + 100mV.
FREQUENCY RESPONSE
The ADS1244’s frequency response for fCLK = 2.4576MHz is
shown in Figure 6. The frequency response repeats at mul-
tiples of 19.2kHz. The overall response is that of a low-pass
filter with a –3dB cutoff frequency of 13.7Hz. As can be seen,
the ADS1244 does a good job attenuating out to 19kHz. For
the best resolution, limit the input bandwidth to below this value
to keep higher frequency noise from affecting performance.
Often a simple RC filter on the ADS1244’s analog inputs is all
that is needed.
VREF is typically AVDD/2, but it can be raised as high as
AVDD. When VREF exceeds AVDD/2, it will not be possible
to reach the full-scale digital output value corresponding to
±2VREF since this would require the analog inputs to exceed
the power supplies. For example, if VREF = AVDD = 5V, the
positive full-scale signal is 10V. The maximum positive input
signal that can be supplied before the ESD diodes begin to turn
on is when AINP = 5.1V and AINN = –0.1V → VIN = 5.2V.
Therefore, it will not be possible to reach the positive (or
negative) full-scale readings in this configuration. The digital
output codes will be limited to approximately one half of the
entire range.
FREQUENCY RESPONSE
f
CLK = 2.4576MHz
0
–20
For best performance, bypass the voltage reference inputs
with a 0.1µF capacitor between VREFP and VREFN. Place
the capacitor as close as possible to the pins.
–40
–60
CLOCK INPUT (CLK)
–80
This digital input supplies the system clock to the ADS1244.
The recommended CLK frequency is 2.4576MHz. This places
the notches of the digital filter at 50Hz and 60Hz and sets the
data rate at 15SPS. The CLK frequency can be increased to
speed up the data rate, but the frequency notches will move
in frequency proportionally. CLK must be left running during
normal operation. It may be turned off during Sleep Mode to
save power, but this is not required. The CLK input may be
driven with 5V logic, regardless of the DVDD or AVDD voltage.
–100
–120
–140
0
9.6
19.2
Frequency (kHz)
FIGURE 6. Frequency Response.
ADS1244
8
SBAS273
www.ti.com
BB [ BURR-BROWN CORPORATION ]
