iPEM
2.1 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR232M64PBG
following two sets of conditions (A or B) must be met to
obtain a stable supply state (stable supply defi ned as
2. For a minimum of 200 µs after stable power nd clock
(ꢁK, ꢁK#), apply NOP or DESELEꢁT commands and
take ꢁKE HIGH.
3. Wait a minimum of 400ns, then issue a PREꢁHARGE
ALL command.
4. Issue an LOAD MODE command to the EMR(2). (To
issue an EMR(2) command, provide LOW to BA0,
provide HIGH to BA1.)
5. Issue a LOAD MODE command to the EMR(3). (To
issue an EMR(3) command, provide HIGH to BA0 and
BA1.)
6. Issue an LOAD MODE command to the EMR to enable
DLL. To issue a DLLENABLE command, provide LOW
to BA1 andA0, provide HIGH to BA0. Bits E7, E8, and
E9 can be set to “0” or “1”; Micron recommends setting
them to “0”.
7. Issue a LOAD MODE command for DLL RESET. 200
cycles of clock input is required to lock the DLL. (To
issue a DLL RESET, provide HIGH to A8 and provide
LOW to BA1, and BA0.) ꢁKE must be HIGH the entire
time.
V
, VꢁꢁQ, VREF, and VTT are between their
mꢁinꢁimum and maximum values as stated in Table20);
A. (single power source) The Vꢁꢁ voltage ramp from
300mV to Vꢁꢁ (MIN) must take no longer than
200ms; during the Vꢁꢁ voltage ramp, |Vꢁꢁ - VꢁꢁQ|
0.3V. Once supply voltage ramping is complete
(when VꢁꢁQ crosses Vꢁꢁ (MIN)), Table 20
specifications apply.
• Vꢁꢁ, V are driven from a single power converter
outputꢁꢁQ
• VTT is limited to 0.95V MAX
• VREF tracks VꢁꢁQꢀ2; VREF must be within
0.3V with respect to VꢁꢁQꢀ2 during supply ramp
time
• VꢁꢁQ > VREF at all times
B. (multiple power sources) V > VꢁꢁQ must be
maintained during supply voltaꢁgꢁe ramping, for both
Aꢁ and Dꢁ levels, until supply voltage ramping
completes (VꢁꢁQ crosses Vꢁꢁ [MIN]). Once supply
voltage ramping is complete, Table 20 specifications
apply.
8. Issue PREꢁHARGEALL command.
9. Issue two or more REFRESH commands, followed
by a dummy WRITE.
• Apply Vꢁꢁ before or at the same time as
VꢁꢁQ; Vꢁꢁ voltage ramp time must be < 200ms
from when Vꢁꢁ ramps from 300mV to Vꢁꢁ (MIN)
• Apply VꢁꢁQ before or at the same time as VTT; the
VꢁꢁQ voltage ramp time from when Vꢁꢁ (MIN) is
achieved to when VꢁꢁQ (MIN) is achieved must be
<500ms; while Vꢁꢁ is ramping, current can be
supplied from Vꢁꢁ through the device to VꢁꢁQ
• VREF must track VꢁꢁQꢀ2, VREF must be within
0.3V with respect to VꢁꢁQꢀ2 during supply ramp
time; VꢁꢁQ > VREF must be met at all times
• Apply VTT; The VTT voltage ramp time from when
VꢁꢁQ (MIN) is achieved to when VTT (MIN) is achieved
must be no greater than 500ms
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR232M64PBG
Rev. 1.3 6/09
5
AUSTIN [ AUSTIN SEMICONDUCTOR ]
