Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 40. Serial Interface Clock/Data Relationship .............................................................................................. 87
Figure 41. Serial Interface Byte Access — Write ................................................................................................... 87
Figure 42. Serial Interface Byte Access — Read ................................................................................................... 87
Figure 43. PCI AD Bus Definition During a Type 0 Configuration Access ............................................................. 88
Figure 44. Type 0 Configuration Read Cycles ....................................................................................................... 89
Figure 45. Type 0 Configuration Write Cycles ....................................................................................................... 89
Figure 46. Zero Wait State Burst Read PCI Bus Transfer (S5335 as Initiator) ...................................................... 94
Figure 47. Single Data Phase PCI Bus Read of S5335 Registers (S5335 as Target) ........................................... 95
Figure 48. Burst PCI Bus Read Attempt to S5335 Registers (S5335 as Target) ................................................... 95
Figure 49. Zero Wait State Burst Write PCI Bus Transfer (S5335 as Initiator) ...................................................... 96
Figure 50. Single Data Phase PCI Bus Write of S5335 Registers (S5335 as Target) ........................................... 97
Figure 51. Master-Initiated, Normal Completion (S5335 as either Target or Initiator) ........................................... 97
Figure 52. Master Initiated Termination Due to Preemption and Latency Timer Active (S5335 as Master) .......... 98
Figure 53. Master Initiated Termination Due to Preemption and Latency Timer Expired (S5335 as Master) ........ 98
Figure 54. Master Abort, No Response ................................................................................................................. 99
Figure 55. Target Disconnect Example 1 (IRDY# deasserted) ............................................................................ 100
Figure 56. Target Disconnect Example 2 (IRDY# asserted) ................................................................................ 100
Figure 57. Target-Initiated Retry .......................................................................................................................... 101
Figure 58. Target Abort Example ......................................................................................................................... 102
Figure 59. PCI Bus Arbitration and S5335 Bus Ownership Example ................................................................... 102
Figure 60. PCI Bus Access Latency Components ............................................................................................... 103
Figure 61. Engaging the LOCK# Signal ............................................................................................................... 104
Figure 62. Access to a Locked Target by its Owner ............................................................................................ 105
Figure 63. Access Attempt to a Locked Target .................................................................................................... 105
Figure 64. Error Reporting Signals ...................................................................................................................... 106
Figure 65. Asynchronous Add-On Operation Register Read ............................................................................... 109
Figure 66. Asynchronous Add-On Operation Register Write ............................................................................... 109
Figure 67. Synchronous FIFO or Pass-Thru Data Register Read ....................................................................... 110
Figure 68. Synchronous FIFO or Pass-Thru Data Register Write ........................................................................ 110
Figure 69. nv Memory Read Operation ................................................................................................................ 115
Figure 70. nv Memory Write Operation ................................................................................................................ 116
Figure 71. Block Diagram - PCI to Add-On Mailbox Register .............................................................................. 117
Figure 72. Block Diagram - Add-On to PCI Mailbox Register .............................................................................. 117
Figure 73. INTCSR FIFO Advance and Endian Control Bits ................................................................................ 124
Figure 74. 16-bit Endian Conversion ................................................................................................................... 125
Figure 75. 32-bit Endian Conversion ................................................................................................................... 125
Figure 76. 64-bit Endian Conversion ................................................................................................................... 126
Figure 77. PCI Read from a Full S5335 FIFO ...................................................................................................... 130
Figure 78. PCI Read from an Empty S5335 FIFO (Target Disconnect) ............................................................... 130
Figure 79. PCI Write to an Empty S5335 FIFO .................................................................................................... 131
Figure 80. PCI Write to a Full S5335 FIFO (Target Disconnect) .......................................................................... 131
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DS1657
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