Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Add-On FIFO Direct Access Mode ................................................................................................................ 132
Additional Status/Control Signals for Add-On Initiated Bus Mastering .......................................................... 134
FIFO Generated Add-On Interrupts ............................................................................................................... 135
8-Bit and 16-Bit FIFO Add-On Interfaces ...................................................................................................... 135
CONFIGURATION ............................................................................................................................................... 136
FIFO Setup During Initialization ..................................................................................................................... 136
FIFO Status and Control Bits ......................................................................................................................... 136
PCI Initiated FIFO Bus Mastering Setup ....................................................................................................... 137
PASS-THRU OVERVIEW .................................................................................................................................... 140
FUNCTIONAL DESCRIPTION ............................................................................................................................ 140
Pass-Thru Transfers ...................................................................................................................................... 140
Pass-Thru Status/Control Signals ................................................................................................................. 141
Pass-Thru Add-On Data Bus Sizing .............................................................................................................. 141
BUS INTERFACE ................................................................................................................................................ 141
PCI Bus Interface .......................................................................................................................................... 141
PCI Pass-Thru Single Cycle Accesses .......................................................................................................... 141
PCI Pass-Thru Burst Accesses ..................................................................................................................... 142
PCI Retry Conditions ..................................................................................................................................... 142
PCI Write Retries ........................................................................................................................................... 142
PCI Read Retries ........................................................................................................................................... 143
Add-On Bus Interface .................................................................................................................................... 143
Single Cycle Pass-Thru Writes ...................................................................................................................... 143
Single Cycle Pass-Thru Reads ...................................................................................................................... 147
Pass-Thru Burst Writes ................................................................................................................................. 147
Pass-Thru Burst Reads ................................................................................................................................. 152
Add-On Pass-Thru Disconnect Operation ..................................................................................................... 156
8-Bit and 16-Bit Pass-Thru Add-On Bus Interface ......................................................................................... 157
CONFIGURATION ............................................................................................................................................... 161
S5335 Base Address Register Definition ...................................................................................................... 161
Creating a Pass-Thru Region ........................................................................................................................ 161
Accessing a Pass-Thru Region ..................................................................................................................... 162
ABSOLUTE MAXIMUM RATINGS ...................................................................................................................... 163
DC CHARACTERISTICS ..................................................................................................................................... 163
PCI BUS SIGNALS ............................................................................................................................................. 164
Add-On Bus Signals .......................................................................................................................................... 165
AC CHARACTERISTICS ..................................................................................................................................... 166
PCI Bus Timing .............................................................................................................................................. 166
Add-On Bus Timings ......................................................................................................................................... 168
Synchronous RDFIFO# Timing ..................................................................................................................... 169
Synchronous WRFIFO# Timing ..................................................................................................................... 170
Asynchronous RD# Register Access Timing ................................................................................................. 171
Asynchronous WR# Register Access Timing ................................................................................................ 172
Synchronous RD# FIFO Timing .................................................................................................................... 173
Synchronous Multiple RD# FIFO Timing ....................................................................................................... 174
Synchronous WR# FIFO Timing .................................................................................................................... 175
Synchronous Multiple WR# FIFO Timing ...................................................................................................... 176
Target S5335 Pass-Thru Interface Timing .................................................................................................... 177
AMCC Confidential and Proprietary
DS1657
6
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
