Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
LIST OF FIGURES
Figure 1. S5335 Block Diagram ............................................................................................................................... 2
Figure 2. S5335 Pinout .......................................................................................................................................... 13
Figure 3. PCI and Add-On Local Bus Signal Diagram ........................................................................................... 16
Figure 4. PCI Pass-Thru Operation Diagram ......................................................................................................... 17
Figure 5. FIFO PCI Bus Mastering Operation Diagram ......................................................................................... 18
Figure 6. S5335 Signal Pins .................................................................................................................................. 19
Figure 7. Vendor Identification Register ................................................................................................................. 29
Figure 8. Device Identification Register ................................................................................................................. 30
Figure 9. PCI Command Register .......................................................................................................................... 31
Figure 10. PCI Status Register .............................................................................................................................. 33
Figure 11. Revision Identification Register ............................................................................................................ 35
Figure 12. Class Code Register ............................................................................................................................. 36
Figure 13. Cache Line Size Register ..................................................................................................................... 40
Figure 14. Latency Timer Register ......................................................................................................................... 41
Figure 15. Header Type Register ........................................................................................................................... 42
Figure 16. Built-In Self Test Register ..................................................................................................................... 43
Figure 17. Base Address Register — Memory ....................................................................................................... 45
Figure 18. Base Address Register — I/O ............................................................................................................... 45
Figure 19. Expansion ROM Base Address Register .............................................................................................. 49
Figure 20. Interrupt Line Register .......................................................................................................................... 51
Figure 21. Interrupt Pin Register ............................................................................................................................ 52
Figure 22. Minimum Grant Register ....................................................................................................................... 53
Figure 23. Maximum Latency Register .................................................................................................................. 54
Figure 24. PCI Controlled Bus Master Write Address Register ............................................................................. 57
Figure 25. PCI Controlled Bus Master Write Transfer Count Register ................................................................... 58
Figure 26. PCI Controlled Bus Master Read Address Register ............................................................................. 59
Figure 27. PCI Controlled Bus Master Read Transfer Count Register .................................................................. 60
Figure 28. Mailbox Empty/Full Status Register ...................................................................................................... 61
Figure 29. Interrupt Control/Status Register .......................................................................................................... 63
Figure 30. FIFO Management and Endian Control Byte ........................................................................................ 64
Figure 31. Bus Master Control/Status Register ..................................................................................................... 67
Figure 32. Add-On Controlled Bus Master Write Address Register ....................................................................... 72
Figure 33. Add-On Controlled Bus Master Read Address Register ....................................................................... 74
Figure 34. Add-On Mailbox Empty/Full Status Register ......................................................................................... 75
Figure 35. Add-On Interrupt Control/Status Register ............................................................................................. 77
Figure 36. Add-On General Control/Status Register ............................................................................................. 80
Figure 37. Add-On Controlled Bus Master Write Transfer Count Register ............................................................ 83
Figure 38. Add-On Controlled Bus Master Read Transfer Count Register ............................................................ 84
Figure 39. Serial Interface Definition of Start and Stop .......................................................................................... 87
AMCC Confidential and Proprietary
DS1657
8
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
