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S3018A/H1 参数 Datasheet PDF下载

S3018A/H1图片预览
型号: S3018A/H1
PDF下载: 下载PDF文件 查看货源
内容描述: [Receiver, 1-Func, PQFP52, PLASTIC, QFP-52]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 22 页 / 147 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER  
S3017/S3018  
Serial to Parallel Converter  
OTHER OPERATING MODES  
The Serial to Parallel Converter consists of three 8-bit  
registers. The first is a serial-in, parallel-out shift reg-  
ister, which performs serial to parallel conversion  
clocked by the clock recovery block. The second is  
an 8-bit internal holding register, which transfers data  
from the serial to parallel register on byte boundaries  
as determined by the frame and byte boundary de-  
tection block. On the falling edge of the free running  
POCLK, the data in the holding register is transferred  
to an output holding register which drives POUT[7:0].  
Diagnostic Loopback  
The Diagnostic Loopback consists of alternate serial  
dataoutputs(inthecaseoftheS3017)andinputs(inthe  
case of the S3018).  
On the S3017, the differential PECL output LPDATO  
provides Diagnostic Loopback serial data. When the  
Local Loopback Enable (LOCLPEN) input and  
TSCLKSEL are low, this data output is a replica of  
SERDATO. When LPDATO is connected to the S3018, a  
loopback from the transmitter to the receiver at the serial  
data rate can be set up for diagnostic purposes. When  
LOCLPEN is high and TSCLKSEL is low, LPDATO is  
held in the inactive state, with the positive output high  
andthenegativeoutputlow. Intheinactivestate, there will  
be no interference from the transmitter to the receiver.  
The delay through the Serial to Parallel converter can  
vary from 1.5 to 2.5 byte periods (12 to 20 serial bit  
periods) measured from the first bit of an incoming byte  
to the beginning of the parallel output of that byte.  
The variation in the delay is dependent on the align-  
ment of the internal parallel load timing, which is  
synchronized to the data byte boundaries, with respect  
to the falling edge of POCLK, which is independent of  
the byte boundaries. The advantage of this serial to  
parallel converter is that POCLK is neither truncated  
nor extended during reframe sequences.  
Onthereceiverside,thedifferentialPECLinputLPDATI  
is the Diagnostic Loopback serial data input. When the  
LocalLoopbackEnable(LOCLPEN)inputissetlow,the  
LPDATI input is routed in place of the normal data  
stream (SERDATI).  
Figure 7. Loopback Diagram  
Data In  
S3018  
Data Out  
CLK  
Control  
S3017  
S3018  
S3017  
Data Out  
Data In  
Control  
CLK  
7
December 10, 1999 / Revision B