S3017/S3018
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
This transfer function yields a typical capture time of 16
µs for random incoming NRZ data. A single external
clean-up capacitor is utilized as part of the loop filter.
S3018 RECEIVER
FUNCTIONAL DESIGN
The S3018 receiver chip provides the first stage of
digitalprocessingofareceiveSONETSTS-12bit-serial
stream. It converts the bit-serial 622.08 Mbit/sec data
stream into a 77.76 Mbyte/sec byte-serial data format.
The total loop dynamics of the clock recovery PLL yield a
jitter tolerance which meets, with ample margin, the mini-
mum tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 6.
Clockrecoveryisperformedontheincomingscrambled
NRZ data stream. A 77.76 MHz reference clock is
required for phase locked loop start-up and proper
operation under loss of signal conditions. An integral
prescaler and phase locked loop circuit is used to
multiply this reference to the nominal bit rate.
Backup Reference Generator
The Backup Reference Generator seen in Figure 5 pro-
videsbackupreferenceclocksignalstotheclockrecovery
block when the clock recovery block detects a loss of
signal condition. It contains a counter that divides the
clock output from the clock recovery block down to the
same frequency as the reference clock REFCKINP/N.
A loopback mode is provided for diagnostic loopback
(transmittertoreceiver), whenusedwiththecompatible
S3017 device.
Frame and Byte Boundary Detection
Clock Recovery
The Frame and Byte Boundary Detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. Framing pattern detection is enabled and dis-
abled by the out-of-frame (OOF) input. Detection is
enabled by a rising edge on OOF, and remains enabled
for the duration that OOF is set high. It is disabled when
a framing pattern is detected and OOF is no longer set
high. When framing pattern detection is enabled, the
framing pattern is used to locate byte and frame bound-
ariesintheincomingdatastream(SERDATIorLPDATI).
The timing generator block takes the located byte
boundary and uses it to block the incoming data stream
into bytes for output on the parallel output data bus
(POUT[7:0]). The frame boundary is reported on the
frame pulse (FP) output when any 48-bit pattern match-
ing the framing pattern is detected on the incoming data
stream. Whenframingpatterndetectionisdisabled,the
byte boundary is frozen to the location found when
detection was previously enabled. Only framing pat-
ternsalignedtothefixedbyteboundaryareindicatedon
the FP output.
The Clock Recovery PLL, as shown in the block diagram
inFigure5,generatesaclockthatisatthesamefrequency
as the incoming data bit rate at the SERDATI or LPDATI
inputs. The clock is phase aligned by a PLL so that it
samples the data in the center of the data eye pattern.
The phase relationship between the edge transitions of
thedataandthoseofthegeneratedclockarecompared
byaphase/frequencydiscriminator.Outputpulsesfrom
thediscriminatorindicatetherequireddirectionofphase
corrections. These pulses are smoothed by an integral
loop filter. The output of the loop filter controls the
frequency of the Voltage Controlled Oscillator (VCO),
whichgeneratestherecoveredclock. Frequencystabil-
ity without incoming data is guaranteed by an alternate
reference input (REFCKIN) that the PLL locks onto
when data is lost.
The clock recovery circuit monitors the incoming data
streamforlossofsignal.Iftheincomingdatastreamhas
had no transitions for between 96 and 224 bit times
(depending upon the state of an internal counter at the
timeoflasttransistion),lossofsignalisdeclaredandthe
PLL will switch from locking onto the incoming data to
locking onto the reference clock. Alternatively, the loss-
of-signal(LOS)inputcanbeusedtoforcealoss-of-signal
condition. When set high, LOS squelches the incoming
data stream, and thus causes the PLL to switch its
source of reference within 128 bit times. Loss-of-signal
condition is removed when LOS is low, and good data,
withacceptablepulsedensityandrunlength,returnson
the incoming data stream.
The probability that random data in an STS-12 stream
will generate the 48-bit framing pattern is extremely
small. It is highly improbable that a mimic pattern would
occur within one frame of data. Therefore, the time to
match the first frame pattern and to verify it with down-
stream circuitry, at the next occurrence of the pattern, is
expected to be less than the required 250 µs, even for
extremely high bit error rates.
Once down-stream overhead circuitry has verified that
frame and byte synchronization are correct, the OOF
inputcanbesetlowtodisabletheframesearchprocess
from trying to synchronize to a mimic frame pattern.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transi-
tion density expected in a received SONET data signal.
6
December 10, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
