SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3017/S3018
Timing Generator
The load signal, which latches the data from the parallel
to the serial shift register, has a fixed relationship to
PCLK. If PICLK is tied to PCLK, the PIN[7:0] data
latched into the parallel register will meet the timing
specifications with respect to the load signal. If PICLK
is not tied to PCLK, the delay must meet the timing
requirements shown in Figure 9, and PICLK must be
frequency locked to the reference clock input.
The Timing Generation function, seen in Figure 4,
provides a byte rate version of the transmit serial clock.
This circuitry also provides an internally generated load
signal, which transfers the PIN[7:0] data from the paral-
lel input register to the serial shift register.
The PCLK output is a byte rate version of transmit serial
clock at 77.76 MHz. PCLK is intended for use as a byte
speed clock for upstream multiplexing and overhead
processing circuits. Using PCLK for upstream circuits will
ensure a stable frequency and phase relationship between
the data coming into and leaving the S3017 device.
Figure 6. Clock Recovery Jitter Tolerance
Figure 6. Clock Recovery Jitter Tolerance
Jitter
Amplitude
(Ul p-p)
15
1.5
OC-12
Parallel-to-Serial Converter
Minimum proposed
tolerance
The Parallel-to-Serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first register
latchesthedatafromthePIN[7:0]busontherisingedge
ofPICLK.Thesecondregisterisaparallelloadableshift
register which takes its parallel input from the first
register.
(TA-NWT-000253)
0.15
30
300
Jitter Frequency (Hz)
6.5k
25k 65k 250k
5
December 10, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
