SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
The Frame and Byte boundary Detection function is
not utilized in the E4 operating mode. It is recom-
mended that the OOF input remain low at all times
for E4 operation to avoid spurious realignment of the
byte boundary, and the FP output should be ignored.
OTHER OPERATING MODES
CMI Encoding and Decoding
Coded Mark Inversion format (CMI) ensures at least
one data transition per bit period, thus aiding the
clock recovery process. Zeros are represented by a
Low state for one half a bit period, followed by a
High state for the rest of that bit period. Ones are
represented by a steady Low or High state for a full
bit period. The state of the ones bit period alter-
nates at each occurrence of a one. Figure 7 shows
an example of CMI-encoded data. The STS-3 elec-
trical interface and the E4 interface are specified to
have CMI-encoded data.
Serial to Parallel Converter
The Serial to Parallel Converter consists of three
8-bit registers. The first is a serial-in, parallel-out
shift register, which performs serial to parallel con-
version clocked by the clock generated by the clock
recovery block. The second is an 8-bit internal hold-
ing register, which transfers data from the serial to
parallel register on byte boundaries as determined
by the frame and byte boundary detection block. On
the falling edge of the free running POCLK, the data
in the holding register is transferred to an output
holding register which drives POUT[7:0].
The CMI encoder on the S3005 SETI accepts serial
data from the Parallel-to-Serial converter block at
one half the TSCLK rate. The data is then encoded
into CMI format, and the result is shifted out into the
output selection logic at the TSCLK rate (311.04
MHz for STS-3 electrical, 278.528 MHz for E4). The
MODE[2:0] inputs control whether the CMI encoder
is in the data path. The encoder is only in the data
path when the STS-3 CMI or the E4 CMI modes are
selected. A single CMI violation can be inserted for
diagnostic purposes by applying a low-to-high tran-
sition on DLCV. This violation is either an inverted
zero code or an inversion of the alternating ones
logic level, depending on the state of the data. Sub-
sequent one codes take into account the induced
violation to avoid error multiplication.
The delay through the Serial to Parallel converter can
vary from 1.5 to 2.5 byte periods (12 to 20 serial bit
periods) measured from the first bit of an incoming
byte to the beginning of the parallel output of that byte.
The variation in the delay is dependent on the alignment
of the internal parallel load timing, which is synchro-
nized to the data byte boundaries, with respect to
the falling edge of POCLK, which is independent of
the byte boundaries. The advantage of this serial to
parallel converter is that POCLK is neither truncated
nor extended during reframe sequences.
Figure 7. CMI Encoded Data
Figure 8. Loopback Diagram
Data In
0
0
1
0
1
1
1
0
Data Out
Control
S3006
S3005
CLK
A2
A1
t
S3006
S3005
Data Out
CLK
Data In
Control
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