SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
For applications that provide a high-frequency bit
clock externally, the internal synthesizer may be by-
passed. Reference frequencies of 19.44 MHz, 38.88
MHz, 51.84 MHz, or 77.76 MHz are selectable for
SONET/SDH by the two reference select input pins.
In E4 applications, these same pins can select the
reference frequency from 17.408 MHz, 34.816 MHz,
46.421 MHz, or 69.632 MHz.
S3005 TRANSMITTER FUNCTIONAL
DESCRIPTION
The S3005 SETI transmitter chip performs the serial-
izing stage in the processing of a transmit SONET
STS-12, STS-3, or ITU-T E4 bit serial data stream. It
converts the byte serial data stream to bit serial for-
mat at 622.08, 155.52, or 139.264 Mbit/s depending
on the control settings and reference frequency pro-
vided by the user. A Coded-Mark-Inversion (CMI) is
available for use during 155.52 Mbit/s STS-3 (electri-
cal) and 139.264 Mbit/s E4 operational modes. (See
Other Operating Modes.)
Loopback modes are provided for diagnostic
loopback (transmitter to receiver), or line loopback
(receiver to transmitter) when used with the compat-
ible S3006. (See Other Operating Modes.)
The operating mode is selected by three mode pro-
gramming inputs to be 622.08 Mbit/s, 155.52 Mbit/s,
155.52 Mbit/s with Coded-Mark-Inversion (CMI) en-
coding, or 139.264 Mbit/s with CMI encoding.
A high-frequency bit clock can be generated from a
variety of lower frequency references by using the
integral frequency synthesizer consisting of a phase-
locked loop circuit with an adjustable divider in the loop.
Figure 5. SONET/SDH Receiver Functional Block Diagram
LCV
LOS
8
C
M
I
1:8 SERIAL
POUT[7:0]
TO PARALLEL
TIMING
GEN
OOF
POCLK
FP
FRAME
BYTE
DETECT
DLEB
2
2
M
U
X
RSDP/N
DLDP/N
BACKUP
REFERENCE
GEN
BYTCLKIP
2
2
2
REFCLKP/N
REFSEL[1:0]
MODE[2:0]
LLDP/N
CLOCK
RECOVERY
2
3
LLCLKP/N
LOCKDET
TESTEN
RSTB
TESTRST
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4
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
