SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Backup Reference Generator
The MODE[2:0] inputs select the recovered serial
clock frequency to be 622.08 MHz for STS-12,
311.04 MHz for CMI-encoded STS-3, 278.528 MHz
for CMI-encoded E4, or 155.52 MHz for STS-3 NRZ.
These frequencies are selected as shown in Table 2.
The Backup Reference Generator seen in Figure 5
provides backup reference clock signals to the clock
recovery block when the clock recovery block de-
tects a loss of signal condition. It contains a counter
that divides the clock output from the clock recovery
block down to the same frequency as the reference
clock REFCLK. The modulus of the counter is a
function of the reference clock frequency and the
operating frequency. The frequency of the reference
clock is selected by the REFSEL[1:0] inputs, as
shown in Tables 3 and 4.
The clock recovery circuit monitors the incoming
data stream for loss of signal. If the incoming en-
coded data stream has been low continuously for
4000 to 8000 recovered clock cycles, loss of signal
is declared and the PLL will switch from locking onto
the incoming data to locking onto the reference
clock. Alternatively, the loss-of-signal (LOS) input
can be used to force a loss-of-signal condition.
When active, LOS squelches the incoming data
stream, and causes the PLL to switch its source of
reference. Loss-of-signal condition is removed when
LOS is inactive, and good data, with acceptable
pulse density and run length, returns on the incoming
data stream.
Frame and Byte Boundary Detection
The Frame and Byte Boundary Detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. This pattern occurs in both STS-3 and STS-12.
Framing pattern detection is enabled and disabled
by the out-of-frame (OOF) input. Detection is enabled
by a rising edge on OOF, and remains enabled for
the duration OOF is set high. It is disabled when a
framing pattern is detected and OOF is no longer set
high. When framing pattern detection is enabled, the
framing pattern is used to locate byte and frame
boundaries in the incoming data stream (RSD or
DLD). The timing generator block takes the located
byte boundary and uses it to block the incoming data
stream into bytes for output on the parallel output
data bus (POUT[7:0]). The frame boundary is re-
ported on the frame pulse (FP) output when any
48-bit pattern matching the framing pattern is de-
tected on the incoming data stream. When framing
pattern detection is disabled, the byte boundary is
frozen to the location found when detection was pre-
viously enabled. Only framing patterns aligned to the
fixed byte boundary are indicated on the FP output.
When the test clock enable (TESTEN) input is set
high, the clock recovery block is disabled. The reference
clock (REFCLK) is used as the bit rate clock input in
place of the recovered clock. The frequency of the
REFCLK should be appropriate for the desired data
rate. The reference selection inputs REFSEL[1:0]
have no effect when TESTEN is set high.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET data
signal. This transfer function yields a typical capture
time of 32 µs for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which meets, with ample margin,
the minimum tolerance proposed for SONET equipment
by the T1X1.6/91-022 document, shown in Figure 6.
Figure 6. Clock Recovery Jitter Tolerance
The probability that random data in an STS-3 or
STS-12 stream will generate the 48-bit framing pattern
is extremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. Therefore,
the time to match the first frame pattern and to verify it
with down-stream circuitry, at the next occurrence of
the pattern, is expected to be less than the required
250 µs, even for extremely high bit error rates.
Sinusodal
Input Jitter
Amplitude
15
(UI p-p)
1.5
0.15
Once down-stream overhead circuitry has verified that
frame and byte synchronization are correct, the OOF
input can be set low to disable the frame search process
from trying to synchronize to a mimic frame pattern.
f0
f2
f2
f3
f3
ft
f1
OC/STS
Level
f0
(Hz)
f1
ft
(Hz)
(Hz) (kHz) (kHz)
3
10
10
30
300
300
6.5
25
75
12
30
250
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
7
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
