Classic EPLD Family Data Sheet
Figure 5. Classic Switching Waveforms
Input Mode
tPD1 = tIN + tLAD + tOD
tPD2 = tIO + tIN + tLAD + tOD
t
and t < 3 ns.
F
R
tIO
Inputs are driven at 3 V
for a logic high and
0 V for a logic low.
I/O Pin
tIN
All timing characteristics
are measured at 1.5 V.
Input Pin
tLAD
tCLR
tOD
Logic Array Input
Logic Array Output
Output Pin
Global Clock Mode
tR
tCH
tCL
tF
Global Clock Pin
Global Clock at Register
Data from Logic Array
tIN
tICS
tH
tSU
Array Clock Mode
tR
tACH
tACL
tF
Clock Pin
Clock into Logic Array
tIN
tIC
Clock from Logic Array
tASU
tAH
Data from Logic Array
tFD
Register Output to Logic Array
Output Mode
Clock from Logic Array
Data from Logic Array
Output Pin
tOD
tZX
tXZ
High-Impedance
Tri-State
752
Altera Corporation
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