AS7C256
AS7C256L
DATA RETENTION CHARACTERISTICS
(L Version Only)
Parameter
for Data Retention
Symbol
Test Conditions
Min
Max
Unit
V
V
I
2.0
–
–
V
CC
DR
V
= 2.0V
CC
Data Retention Current
150
–
µA
ns
CCDR
CDR
R
CE ≥ V –0.2V
CC
Chip Enable to Data Retention Time
Operation Recovery Time
Input Leakage Current
t
t
0
V
in ≥ V –0.2V or
CC
t
–
ns
RC
V
in ≤ 0.2V
| I
|
–
1
µA
LI
DATA RETENTION WAVEFORM
(L Version Only)
Data retention mode
DR ≥ 2.0V
V
4.5V
4.5V
V
CC
t
t
R
CDR
V
DR
V
V
CE
IH
IH
AS7C256-07
AC TEST CONDITIONS
– Output load: see Figure B,
Thevenin Equivalent:
except for t
and t
see Figure C.
CLZ
CHZ
168Ω
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 5 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
D
+1.728V
+5V
out
+5V
480Ω
480Ω
D
D
out
out
+3.0V
90%
10%
90%
10%
*including scope
and jig capacitance
255Ω
30 pF*
GND
255Ω
5 pF*
GND
GND
Figure B: Output Load
Figure C: Output Load for t
, t
Figure A: Input Waveform
CLZ CHZ
AS7C256-08
AS7C256-09
AS7C256-10
NOTES
1. During V power-up, a pull-up resistor to V on CE is required to meet I specification.
CC
CC
SB
2. This parameter is sampled and not 100% tested.
3. For test conditions, see AC Test Conditions, Figures A, B, C.
4.
t
and t
are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
CHZ
CLZ
5. This parameter is guaranteed but not tested.
6. WE is HIGH for read cycle.
7. CE and OE are LOW for read cycle.
8. Address valid prior to or coincident with CE transition LOW.
9. All read cycle timings are referenced from the last valid address to the first transitioning address.
10. CE or WE must be HIGH during address transitions.
11. All write cycle timings are referenced from the last valid address to the first transitioning address.
6
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
