TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions 1/
4.5 V < VCC < 5.5 V
-55°C < TC < +125°C
unless otherwise specified
Group A
Subgroups
Device
type
Limits
Max
Unit
Min
3.7
High Level output voltage
Low level output voltage
VOH
VOL
Test one output at a time,
CC = 4.5 V, IOH = -3.2 mA
1, 2, 3
1, 2, 3
All
All
All
V
V
V
Test one output at a time,
CC = 4.5 V, IOL = 4.0 mA
0.4
V
Low level input voltage
High level input voltage
VIL
VIH
1, 2, 3
1, 2, 3
-0.3
2.0
0.8
V
V
01,02,
04,05
VCC +0.3
03
All
2.2
VCC +0.3
25
Standby supply current
IDD
Outputs unloaded,
1, 2, 3
mA
VCC = 5.5 V,
VIN = VCC or GND
Input leakage current
Output leakage current
IIL
VCC = 5.5 V,
IN = VCC or GND
1, 2, 3
1, 2, 3
All
All
-10
-10
10
10
20
µA
µA
pF
V
IOZ
VCC = 5.5 V,
VO = VCC or GND
I/O terminal capacitance
Functional tests
CI/O
See 4.4.1c, f= 1.0 Mhz,
4
All
All
VOUT = 0 V
FT 2/
See 4.4.1e, VO = 0 V,
CC = 4.5 V
7, 8A, 8B
9, 10, 11
V
Binning circuit delay
tPBLH,
tPBHL
See figure 3, VIL = 0 V,
ns
01
02
03
04
05
200
170
160
120
102
V
V
IH = 3.0 V, VCC = 4.5 V,
OUT = 1.5 V 3/
1/ All tests shall be performed under the worst case condition unless otherwise specified. Devices supplied to this drawing will
meet levels M, D, L, R, and F, of irradiation. However, this device is only tested at the "F" level. Pre and post irradiation
values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for
any RHA level, TA = +25°C.
2/ Devices are functionally tested using a serial scan test method. Data is shifted into the SDI pin and the DCLK pin is used
as a clock. The data is used to drive the inputs of the internal logic and I/O modules, allowing a complete functional test to
be performed. The outputs of the module can be read by shifting out the output response or by monitoring the PRA, PRB,
or SDO pins. These tests form a part of the manufacturer's test tape and shall be maintained and available at the approved
source(s) of supply upon request by DSCC or the OEM.
3/ Binning circuit delay is defined as the input-to-output delay of a special path called the "binning circuit". The binning circuit
consists of one input buffer plus 16 combinatorial logic modules plus one output buffer. The logic modules are distributed
along the left side of the device. These modules are configured as non-inverting buffers and are connected through
programmed antifuses with typical capacitive loading.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
5
DSCC FORM 2234
APR 97
ACTEL [ Actel Corporation ]
