Core1553BBC MIL-STD-1553B Bus Controller
Core1553BBC Device Requirements
The Core1553BBC can be implemented in several Actel FPGA devices. Table 1 shows typical utilization figures for the
Core1553BBC implemented in these devices.
Table 1 • Device Utilization
Cells or Tiles
Family
Fusion
Combinatorial
1773
Sequential
558
Total
2331
2331
2810
1656
1656
1704
1696
Device
AFS600
Utilization
17%
ProASIC3/E
ProASICPLUS
Axcelerator
RTAX-S
1773
558
A3PE600
17%
2250
560
APA150-STD
AX500-STD
RTAX250-STD
A54SX32A-STD
RT54SX32S-STD
46%
1072
584
20%
1072
584
9%
SX-A
1115
589
56%
RTSX-S
1098
598
57%
The Core1553BBC clock rate can be programmed to 12,
16, 20, or 24 MHz. All Actel device families listed in
Table 1 easily meet this performance requirement.
When implemented in ProASICPLUS or Axcelerator
devices, the Core1553BBC can connect directly to the
internal FPGA memory blocks, eliminating the need for
external memories.
MIL-STD-1553B Bus Overview
The MIL-STD-1553B bus is a differential serial bus used in
military and space equipment. It is comprised of multiple
redundant bus connections and communicates at 1MB
per second.
The bus has a single active bus controller (BC) and up to
31 remote terminals (RTs). The BC manages all data
transfers on the bus using the command and status
protocol. The bus controller initiates every transfer by
sending a command word and data if required. The
selected RT will respond with a status word and data if
required.
Core1553BBC Verification and
Compliance
Core1553BBC is based upon the Actel Core1553BRT,
which has been fully verified against the RT validation
Test Plan (MIL-HDBK-1553A, Appendix A). This ensures
that the 1553B encoders and decoders are fully
compliant to the 1553B specification. The actual bus
controller function has been extensively verified in both
simulation and hardware. Core1553BBC has been
implemented on an A54SX32A-STD part connected to
external transceivers and memory.
The 1553B command word contains a five-bit RT address,
a transmit or receive bit, a five-bit sub-address and a five-
bit word count. This allows for 32 RTs on the bus.
However, since RT address 31 is used to indicate a
broadcast transfer, only 31 RTs may be connected. Each
RT has 30 sub-addresses reserved for data transfers. The
other two sub-addresses (0 and 31) are reserved for
mode codes. Data transfers contain up to (32) 16-bit data
words. Mode code command words are used for bus
control functions such as synchronization.
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ACTEL [ Actel Corporation ]
