Core1553BBC MIL-STD-1553B Bus Controller
and transmitted on the 1553B bus. Data received is
written to the memory. The core can be configured
directly to connect to synchronous or asynchronous
memory devices.
General Description
The Core1553BBC provides a complete, MIL-STD-1553B
Bus Controller (BC). A typical system implementation
using the Core1553BBC is shown in Figure 1.
The core consists of five main blocks: the 1553B encoder,
the 1553B decoder, a protocol controller block, a CPU
interface, and a backend interface (Figure 2).
Core1553BBC reads message descriptor blocks from the
memory and generates messages that are transmitted on
the 1553B bus. Data words are read from the memory
BUSAINEN
RCVSTBA
RXDAIN
RXDAIN
BUSAINP
BUSAINN
Memory
BUSAOUTINH
BUSAOUTP
BUSAOUTN
TXINHA
TXDAIN
TXDAIN
Glue
Logic
Transceiver
(Not Included)
BUSBINEN
BUSBINP
BUSBIN
RCVSTBA
RXDBIN
RXDBIN
CPU
BUSAOUTINH
BUSBOUTP
BUSBOUTN
TXINHA
TXDBIN
TXDBIN
Core1553BBC
Actel FPGA
Figure 1 • Typical Core1553BBC System
Encoder
Decoder
BusA
BusB
Protocol
Controller
Backend
Interface
Memory
64K*16
CPU
Interface
and
Registers
Core1553BBC
Figure 2 • Core1553BBC BC Block Diagram
2
v4.0
ACTEL [ Actel Corporation ]
