Core1553BBC MIL-STD-1553B Bus Controller
Miscellaneous I/O
Several inputs are used to modify the core functionality to simplify integration in the application. These inputs should
be tied to logic '0' or logic '1' as appropriate (Table 7).
Table 6 • Memory Access Requirements
CPUMEMEN CLK Speed MHz Memory Access Time
0
0
0
0
1
1
1
1
12
16
20
24
12
16
20
24
9.58µs
9.68µs
9.75µs
9.79µs
4.58µs
4.68µs
4.75µs
4.79µs
Table 7 • Miscellaneous I/O
Name
Type Description
ASYNCIF
In
When '1,' the backend interface is in asynchronous mode. When '0,' the backend interface is in synchronous
mode.
CPUMEMEN
In
When '1,' the CPU interface has access to the backend memory. When '0,' the CPU cannot access the
backend memory through the core. This must be set to '0' if the core shares the CPU memory, i.e. the CPU
and memory buses are connected to the same system bus.
Bus Controller Registers
The bus controller has nine internal registers used to control the bus controller operation and provide status
information (Table 8).
Table 8 • Bus Controller Registers
Address
000
Name
CONTROL
STATUS
SETUP
Type
W
Size
[3:0]
Function
Allows the CPU to control the BC
Provides status information
BC setup register
000
R
[15:0]
[15:0]
[15:0]
001
RW
RW
010
LISTPTR
Current LISTPTR value. The address of the current instruction being
executed. At the start of operation, the CPU should set this to the point
at the first instruction. This value will automatically step through the BC
instruction list.
011
100
MSGPTR
CLOCK
R
[15:0]
[15:0]
Current MSGPTR value. Provides the address of the message block
being processed.
RW
BC internal clock value
This 16-bit value counts up at a 1µs, 4µs, 8µs, or 32µs rate. This gives a
maximum timer value of 2 seconds. The CPU may directly load the
counter.
101
ASYNCPTR
RW
[15:0]
Asynchronous list pointer
Provides a pointer to a list of messages that will be processed when
started by the ASYNC message list bit in the control register.
v4.0
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ACTEL [ Actel Corporation ]
