LIST OF FIGURES (2/8)
Figure No.
Title
Page
7-9
Main System Clock Stop Function .......................................................................................... 150
System Clock and CPU Clock Switching ................................................................................ 153
7-10
8-1
16-bit Timer/Event Counter Block Diagram ............................................................................ 160
16-bit Timer/Event Counter Output Control Circuit Block Diagram ....................................... 161
Timer Clock Selection Register 0 Format ............................................................................... 165
16-bit Timer Mode Control Register Format ........................................................................... 166
Capture/Compare Control Register 0 Format......................................................................... 167
16-bit Timer Output Control Register Format ......................................................................... 168
Port Mode Register 3 Format .................................................................................................. 169
External Interrupt Mode Register 0 Format ............................................................................ 170
Sampling Clock Select Register Format ................................................................................. 171
Control Register Settings for Interval Timer Operation .......................................................... 172
Interval Timer Configuration Diagram ..................................................................................... 173
Interval Timer Operation Timings ............................................................................................ 173
Control Register Settings for PWM Output Operation ........................................................... 175
Example of D/A Converter Configuration with PWM Output ................................................. 176
TV Tuner Application Circuit Example .................................................................................... 176
Control Register Settings for PPG Output Operation............................................................. 177
Control Register Settings for Pulse Width Measurement with Free-running Counter
and One Capture Register....................................................................................................... 178
Configuration Diagram for Pulse Width Measurement by Free-running Counter ................. 179
Timing of Pulse Width Measurement Operation by Free-running Counter and
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
One Capture Register (with Both Edges Specified) ............................................................... 179
Control Register Settings for Two Pulse Width Measurements with
8-20
8-21
8-22
8-23
Free-running Counter ............................................................................................................... 180
Timing of Pulse Width Measurement Operation with Free-running Counter
(with Both Edges Specified) .................................................................................................... 181
Control Register Settings for Pulse Width Measurement with Free-running Counter
and Two Capture Registers ..................................................................................................... 182
Timing of Pulse Width Measurement Operation by Free-running Counter and
Two Capture Registers (with Rising Edge Specified) ............................................................ 183
Control Register Settings for Pulse Width Measurement by Means of Restart.................... 184
Timing of Pulse Width Measurement Operation by Means of Restart
8-24
8-25
(with Rising Edge Specified) ................................................................................................... 184
Control Register Settings in External Event Counter Mode .................................................. 185
External Event Counter Configuration Diagram ..................................................................... 186
External Event Counter Operation Timings (with Rising Edge Specified) ............................ 186
Control Register Settings in Square-wave Output Mode ....................................................... 187
Square-wave Output Operation Timing................................................................................... 188
Control Register Settings for One-shot Pulse Output Operation Using Software Trigger ... 189
Timing of One-shot Pulse Output Operation Using Software Trigger ................................... 190
Control Register Settings for One-shot Pulse Output Operation Using External Trigger .... 191
8-26
8-27
8-28
8-29
8-30
8-31
8-32
8-33
24
ETC [ ETC ]
