Turbo IC, Inc.
24C01/24C02
PRODUCT INTRODUCTION
CURRENT ADDRESS READ:
The internal memory address counter of the Turbo IC 24C01/
24C02 contains the last memory address accessed during
the previous read or write operation, incremented by one. To
start the current address read operation, the master issues
a start condition, followed by the device address byte 1010
(A2) (A1) (A0) 1. The Turbo IC 24C01/24C02 responds with
an acknowledge by pulling the SDA bus low, and then seri-
ally shifts out the data byte accessed from memory at the
location corresponding to the memory address counter. The
master does not acknowledge, then sends a stop condition
to terminate the read operation. It is noted that the memory
address counter is incremented by one after the data byte is
shifted out.
RANDOM ADDRESS READ:
The master starts with a dummy write operation (one with no
data bytes) to load the internal memory address counter by
first issuing a start condition, followed by the device address
byte 1010 (A2) (A1) (A0) 0, followed by the memory address
bytes. Following the acknowledge from the Turbo IC 24C01/
24C02, the master starts the current read operation by issu-
ing a start condition, followed by the device address byte
1010 (A2) (A1) (A0) 1. The Turbo IC 24C01/24C02 responds
with
Current Address Read
S
T
A
R
T
SDA LINE
M
S
B
L RA
S / C
B WK
N
O
A
C
K
an acknowledge by pulling the SDA bus low, and then seri-
ally shifts out the data byte accessed from memory at the
location corresponding to the memory address counter. The
master does not acknowledge, then sends a stop condition
to terminate the read operation. It is noted that the memory
address counter is incremented by one after the data byte is
shifted out.
SEQUENTIAL READ:
The sequential read is initiated by either a current address
read or random address read. After the Turbo IC 24C01/
24C02 serially shifts out the first data byte, the master ac-
knowledges by pulling the SDA bus low, indicating that it re-
quires additional data bytes. After the data byte is shifted
out, the Turbo IC 24C01/24C02 increments the memory ad-
dress counter by one. Then the Turbo IC 24C01/24C02 shifts
out the next data byte. The sequential reads continues for as
long as the master keeps acknowledging. When the memory
address counter is at the last memory location, the counter
will ‘roll-over’ when incremented by one to the first location in
memory (address zero). The master terminates the sequen-
tial read operation by not acknowledging, then sends a stop
condition.
DEVICE
ADDRESS
R
E
A
D
DATA
S
T
O
P
Random Read
S
T
A
R
T
SDA LINE
M
S
B
DEVICE
ADDRESS
W
R
I
T
E
WORD
ADDRESS N
//
DEVICE
ADDRESS
R
E
A
D
DATA n
S
T
O
P
L RA
S / C
B WK
//
A
C
K
A
C
K
N
O
A
C
K
DUMMY WRITE
6
ETC [ ETC ]
