SigmaTel, Inc.
Data Sheet
STAC9721
9.2 Warm Reset
. Warm Reset
Figure 14
Tsync_high
Tsync_2clk
SYNC
BIT_CLK
. Warm Reset
Symbol
Table 24
Parameter
Min
Typ
Max
Units
SYNC active high pulse width
SYNC inactive to BIT_CLK startup delay
Tsync_high
Tsync2clk
1.0
162.8
1.3
-
-
-
us
ns
9.3 Clocks
. Clocks
Figure 15
Tclk_low
Tclk_high
BIT_CLK
SYNC
Tclk_period
Tsync_low
Tsync_high
Tsync_period
. Clocks
Table 25
Parameter
Symbol
Min
Typ
Max
Units
BIT_CLK frequency
BIT_CLK period
-
-
12.288
81.4
-
-
-
MHz
ns
Tclk_period
BIT_CLK output jitter
BLT_CLK high pulsewidth (note 1)
BIT_CLK low pulse width (note 1)
SYNC frequency
-
750
45
45
-
ps
Tclk_high
Tclk_low
36
36
-
40.7
40.7
48.0
20.8
1.3
ns
ns
kHz
us
SYNC period
SYNC high pulse width
SYNC low_pulse width
Tsync_period
Tsync_high
Tsync_low
-
-
-
-
us
us
-
19.5
-
Notes: 1) Worst case duty cycle restricted to 40/60.
04/07/00
34
04/07/00
ETC [ ETC ]
