Ver 1.3
PRELIMINARY
EAGLE
3.2 Pin Mux
4 IOs are multiplexed into Pin Mux. Certain pins consist of Multi-IOs. These Multi-IOs should be carefully set. For
example, EXT_IRQ[2] pin is multiplexed with BEx[1] pin in PINMUX0 register, D[28] pin in PINMUX2 register, and
another Pin Mux register pin. When EXT_IRQ[2] pin in PINMUX0 register is used, other PINMUX register pins should be
set instead of EXT_IRQ[2] pin . The Multi-IOs are summarized as follows:
EXT_IRQ[7:0], GUN[1:0], KEY_IN[4:0], KEY_OUT[4:0], UART_Tx[3:2], UART_Rx[3:2], DMA_REQx[0],
DMA_ACKx[0], DEC_DIN[7:0], DEC_ACTIVE, HSYNC_IN, VSYNC_IN, DEC_FIELD, I2S_SDO, I2S_SDI, I2S_SCK,
I2S_LRCK, I2S_MCLK, SND_SDO, SND_SCK, SND_LRCK, SND_MCLK, USB_ovrcur, USB_prtpwr
3.2.1 Pin Mux Control Register 0 (PINMUX0)
Address : FFE0 0010h
Bit
R/W
R/W
Description
10 : EXT_IRQ[2]
Default Value
00 : BEx[1]
01 :
0000 0h
31 : 30
11 : GPIO[15]
00 : NDFL_CLE
01 :
00 : NDFL_ALE
01 :
00 : A[23]
01 : GUN[1]
00 : A[22]
01 : GUN[0]
00 : A[21]
01 :
00 : A[20]
01 :
00 : A[19]
01 :
00 : A[18]
01 :
00 : A[17]
01 :
10 : A[25]
11 : GPIO[14]
10 : A[24]
29 : 28
27 : 26
25 : 24
23 : 22
21 : 20
19 : 18
17 : 16
15 : 14
11 : GPIO[13]
10 : EXT_IRQ[4]
11 : GPIO[12]
10 : EXT_IRQ[5]
11 : GPIO[11]
10 : EXT_IRQ[6]
11 : GPIO[10]
10 : EXT_IRQ[7]
11 : GPIO[9]
10 :
11 : GPIO[8]
10 :
11 : GPIO[7]
10 :
11 : GPIO[6]
13 : 12
11 :6
5 : 4
R
R/W
Reserved
00 : TA[9]
01 :
-
10 :
11 : GPIO[2]
00h
00 : TA[8]
01 :
00 : TA[7]
01 :
10 :
11 : GPIO[1]
10 :
3 : 2
1 : 0
11 : GPIO[0]
45
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
