Ver 1.3
PRELIMINARY
EAGLE
3.32
JTAG of EAGLE
3.32.1 Features
- Supports mandatory instruction ( Sample/Preload, EXTEST , Bypass, IDCODE)
- Supports CPU debug instruction (EISC debug )
3.32.2 Block diagram
Figure 3-64 JTAG Block Diagram
3.32.3 Description
JTAG is composed of instruction register, 4 data registers(Bypass register, IDCODE register EISC Debug register,
boundary scan register) and Tap controller
3.32.3.1 JTAG Instruction
Instruction register and data registers are connected to TDI. Every register output is transferred through Mux and TDO and
the contents of instruction register selects one register among the 4 data registers.
Instruction
Sample / Preload
Bypass
Binary code
0011
Selected register
Boundary scan register
Bypass register
1111
EXTEST
IDCODE
0000
1010
Boundary scan register
IDCODE register
EISC Debug
1001 / 1011
EISC Debug register
229
CONFIDENTIAL
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