EAGLE
PRELIMINARY
Ver 1.3
3.13.4 Control Registers
The Control Registers below are used to control each Multi-Standard Video Encoder.
Multi-Standard Video Control Registers map
Name
Bits Default
Function Description
Etc.
Video Encoder Control Registers
Enc_Mode
Enc_Hue
8
8
8
8
8
8
8
8
8’h00
8’h00
8’h40
8’h40
8’h00
8’h80
8’h80
8’h80
Encoder Mode control register
Encoder Hue adjust control register
Encoder Vertical Phase control register
Encoder Horizontal Phase control register
Encoder Test control register
Enc_VPC
Enc_VPC
Enc_Test
Enc_Brightness
Enc_Contrast
Enc_Saturation
Encoder Brightness register
Encoder Contrast register
Encoder Saturation register
3.13.5 Enc_Mode Register (ENCMODE)
Address : FFE0 4400h
Bit
R/W
Description
Default Value
31 : 8
R
Reserved
-
Encoder Input Video Data Select
: This is a control register for selecting the format of Input Component. If “10”
is selected, the internal Test Pattern (Color Bar Pattern) is displayed. If “00”
7 : 6
R/W
is selected, the input format is set to RGB and converted to YCbCr format
00b
through Color Space Converter, before generation of CVBS signal.
00 : RGB Data Select
10 : Internal Color Bar Select
Software Reset
: It is used to Disable or Enable the Video Encoder.
0 : Software Reset
1 : Software Set
Pedestal enable
5
4
R/W
R/W
0b
0b
: In NTSC, Pedestal Level to 7.5IRE exists, but the Pedestal Level does not
exist in NTCS-J. This register controls the on/off operation of Pedestal
Level.
0 : Pedestal Off
1 : Pedestal On
Chrominance Low-pass filter bandwidth
: This controls the bandwidth of CLPF. Larger Color bandwidth contains more
color data in CVBS.
3 : 2
R/W
R/W
00 : 1.2Mhz
01 : 1.0Mhz
10 : 0.8Mhz
11 : 0.6Mhz
00b
00b
132
Format
: This register selects the System of the CVBS to be generated. Timing and
FSC are automatically generated for each corresponding System.
00 : NTSC
10 : PAL-M
X1 : PAL
1 : 0
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