MAX 3000A Programmable Logic Device Family Data Sheet
Figure 2. MAX 3000A Macrocell
LAB Local Array
Global
Clear
Parallel Logic
Expanders
(from other
macrocells)
Global
Clocks
2
Programmable
Register
Register
Bypass
to I/O
Control
Block
PRN
D/T Q
Product-
Term
Select
Matrix
VCC
Clock/
Enable
Select
ENA
CLRN
Clear
Select
Shared Logic
Expanders
36 Signals
from PIA
16 Expander
Product Terms
to PIA
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the
OR
and
XOR
gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
s
s
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
The MAX+PLUS II development system automatically optimizes
product-term allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
MAX+PLUS II software then selects the most efficient flipflop operation
for each registered function to optimize resource utilization.
6
Altera Corporation
ETC [ ETC ]
