MAX 3000A Programmable Logic Device Family Data Sheet
Figure 1. MAX 3000A Device Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
INPUT/GCLRn
6 Output Enables
LAB A
36
36
6 Output Enables
LAB B
6 to 16 I/O
6 to 16
I/O
Control
Block
Macrocells
1 to 16
16
Macrocells
17 to 32
6 to 16
I/O
Control
Block
6 to 16 I/O
16
6
6 to 16
6 to 16
6
LAB C
PIA
Macrocells
33 to 48
16
36
36
LAB D
6 to 16 I/O
I/O
Control
Block
6 to 16
Macrocells
49 to 64
6 to 16
I/O
Control
Block
6 to 16 I/O
16
6
6 to 16
6 to 16
6
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of
high-performance LABs. LABs consist of 16-macrocell arrays, as shown in
Figure 1.
Multiple LABs are linked together via the PIA, a global bus that
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
s
s
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Macrocells
MAX 3000A macrocells can be individually configured for either
sequential or combinatorial logic operation. Macrocells consist of three
functional blocks: logic array, product-term select matrix, and
programmable register.
Figure 2
shows a MAX 3000A macrocell.
Altera Corporation
5
ETC [ ETC ]
