MAX 3000A Programmable Logic Device Family Data Sheet
...and More
Features
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Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Programmable power-saving mode for a power reduction of over
50% in each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
Programmable security bit for protection of proprietary designs
Enhanced architectural features, including:
–
6 pin- or logic-driven output enable signals
–
Two global clock signals with optional inversion
–
Enhanced interconnect resources for improved routability
–
Programmable output slew-rate control
Software design support and automatic place-and-route provided by
the Altera
®
MAX+PLUS
®
II development system for Windows-based
PCs and Sun SPARCstations, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
third-party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with the Altera master programming unit
(MPU), MasterBlaster
TM
communications cable, ByteBlasterMV
TM
parallel port download cable, BitBlaster
TM
serial download cable as
well as programming hardware from third-party manufacturers and
any in-circuit tester that supports Jam
TM
Standard Test and
Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
General
Description
MAX 3000A devices are low-cost, high-performance devices based on the
Altera MAX architecture. Fabricated with advanced CMOS technology,
the EEPROM-based MAX 3000A devices operate with a 3.3-V supply
voltage and provide 600 to 5,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices
in the -4, -5, -6, -7, and -10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG)
PCI Local Bus
Specification, Revision 2.2.
See
Table 2.
2
Altera Corporation