MAX 3000A
®
Programmable Logic
Device Family
Data Sheet
September 2000, ver. 1.1
Features...
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High-performance, low-cost CMOS EEPROM-based programmable
logic devices (PLDs) built on a Multiple Array MatriX (MAX
®
)
architecture (see
Table 1)
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
Enhanced ISP features:
–
Enhanced ISP algorithm for faster programming
–
ISP_Done bit to ensure complete programming
–
Pull-up resistor on I/O pins during in-system programming
High-density PLDs ranging from 600 to 5,000 usable gates
4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
MultiVolt
TM
I/O interface enabling the device core to run at 3.3 V,
while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic
levels
Pin counts ranging from 44 to 208 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), and plastic J-lead chip carrier
(PLCC) packages
Hot-socketing support
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
PCI compatible
Bus-friendly architecture including programmable slew-rate control
Open-drain output option
Table 1. MAX 3000A Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
PD
(ns)
t
SU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
Altera Corporation
A-DS-M3000A-01.1
EPM3032A
600
32
2
34
4.5
2.9
3.0
227.3
EPM3064A
1,250
64
4
66
4.5
2.8
3.1
222.2
EPM3128A
2,500
128
8
96
5.0
3.3
3.4
192.3
EPM3256A
5,000
256
16
158
5.5
3.9
3.5
172.4
1