80C186XL/80C188XL
Table 3. Pin Descriptions (Continued)
Pin
Pin
Input
Type
Output
Pin Description
Name
Type
States
UCS
I/O
A(L)
H(1)
R(WH)
Upper Memory Chip Select is an active LOW output
whenever a memory reference is made to the defined
upper portion (1K–256K block) of memory. The
address range activating UCS is software
programmable.
UCS and LCS are sampled upon the rising edge of
RES. If both pins are held low, the processor will enter
ONCE Mode. In ONCE Mode all pins assume a high
impedance state and remain so until a subsequent
RESET. UCS has a weak internal pullup that is active
during RESET to ensure that the processor does not
enter ONCE Mode inadvertently.
LCS
I/O
A(L)
H(1)
R(WH)
Lower Memory Chip Select is active LOW whenever a
memory reference is made to the defined lower portion
(1K–256K) of memory. The address range activating
LCS is software programmable.
UCS and LCS are sampled upon the rising edge of
RES. If both pins are held low, the processor will enter
ONCE Mode. In ONCE Mode all pins assume a high
impedance state and remain so until a subsequent
RESET. LCS has a weak internal pullup that is active
only during RESET to ensure that the processor does
not enter ONCE mode inadvertently.
MCS0/PEREQ
MCS1/ERROR
I/O
O
A(L)
H(1)
R(WH)
Mid-Range Memory Chip Select signals are active LOW
when a memory reference is made to the defined mid-
range portion of memory (8K–512K). The address
ranges activating MCS0–3 are software programmable.
MCS2
MCS3/NPS
H(1)
R(1)
On the 80C186XL, in Enhanced Mode, MCS0 becomes
a PEREQ input (Processor Extension Request). When
connected to the Math Coprocessor, this input is used
to signal the 80C186XL when to make numeric data
transfers to and from the coprocessor. MCS3 becomes
NPS (Numeric Processor Select) which may only be
activated by communication to the 80C187. MCS1
becomes ERROR in Enhanced Mode and is used to
signal numerics coprocessor errors.
PCS0
PCS1
PCS2
PCS3
PCS4
O
O
H(1)
R(1)
Peripheral Chip Select signals 0–4 are active LOW
when a reference is made to the defined peripheral
area (64 Kbyte I/O or 1 MByte memory space). The
address ranges activating PCS0–4 are software
programmable.
PCS5/A1
H(1)/H(X)
R(1)
Peripheral Chip Select 5 or Latched A1 may be
programmed to provide a sixth peripheral chip select, or
to provide an internally latched A1 signal. The address
range activating PCS5 is software-programmable.
PCS5/A1 does not float during bus HOLD. When
programmed to provide latched A1, this pin will retain
the previously latched value during HOLD.
NOTE:
Pin names in parentheses apply to the 80C188XL.
14
ETC [ ETC ]
