24AA02/24LC02B
7.0
READ OPERATION
7.3
Sequential Read
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘
1
’. There are three basic types
of read operations: current address read, random read
and sequential read.
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24XX02 transmits the
first data byte, the master issues an acknowledge as
opposed to a STOP condition in a random read. This
directs the 24XX02 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24XX02 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
7.1
Current Address Read
The 24XX02 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘
1
’. Therefore, if the previous access
(either a read or write operation) was to address
n
, the
next current address read operation would access data
from address
n + 1
. Upon receipt of the slave address
with R/W bit set to ‘
1
’, the 24XX02 issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer but does generate a
STOP condition and the 24XX02 discontinues trans-
mission (Figure 7-1).
7.4
Noise Protection
The 24XX02 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX02 as part of a write operation. After the word
address is sent, the master generates a START condi-
tion following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W bit set to a ‘
1
’. The 24XX02 will
then issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a STOP condition and the 24XX02 dis-
continues transmission (Figure 7-2).
FIGURE 7-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
T
S
A
C
K
N
O
A
C
K
CONTROL
BYTE
S
T
O
P
P
DATA (n)
SDA LINE
BUS ACTIVITY
2002 Microchip Technology Inc.
DS21709A-page 9
ETC [ ETC ]
