TP6312
1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER
Pin Configuration (Top View)
Grid 4
Grid 3
Grid 2
Grid 1
VDD
Seg8
Seg7
Seg6 /KS6
Seg5 /KS5
Seg4 /KS4
Seg3 /KS3
Seg2 /KS2
Seg1 /KS1
VDD
LED 4
LED 3
LED 2
LED 1
VSS
KEY 4
OSC
KEY 3
Use all the power pins.
Pin Description
Pin No
Symbol
Pin Name
Description
Inputs serial data at rising edge of shift clock,
starting from the lower bit.
6
DIN
Date input
Outputs serial data at falling edge of shift clock,
starting from the lower bit. This is N-ch open-drain
output pin.
5
9
DOUT
STB
Date output
Strobe
Initializes the serial interface at rising or falling edge
to make TP6312 waiting for reception of command.
Data input after STB has fallen is processed as
command. While command data is processed,
current processing is stopped and serial interface is
initialized. While STB is high, CLK is ignored.
Reads serial data at rising edge, and outputs data at
falling edge.
8
CLK
Clock input
Oscillator pin
Connects a resistor to this pin to determine the
oscillation frequency to this pin.
44
OSC
Seg1/KS1 to
Seg6/KS6
Segment output pins (Dual function as Key source).
15 to 20
21 to 25
37 to 32
High-voltage output
High-voltage output
(Segment)
High-voltage output
(Grid)
Segment output pins.
Grid output pins.
Seg7 to Seg11
Grid1 to Grid6
Seg11/Grid11 to
Seg16/Grid7
LED1 to LED4
High-voltage output
(Segment/grid)
LED output
These pins are selectable for segment or grid
driving.
CMOS output. +20 mA max.
26, 28 to 31
42 to 39
Data input to these pins is latched at the end of
display cycle.
These pins constitute 4-bit general-purpose input
port.
10 to 13
Key1 to Key4
SW1 to SW4
Key data input
Switch input
1 to 4
5V ± 10%
Connect this pin to system GND.
VDD – 35 V max
14, 38
7, 43
27
VDD
VSS
VEE
Logic power
Logic ground
Pull-down level
Version 1.1
September 2003
Page 2 of 9
http://www.topro.com.tw
ETC [ ETC ]
