DM9000A
Ethernet Controller with General Processor Interface
6.8 Receive Overflow Counter Register ( 07H )……………………………………..…………….…………..………17
6.9 Back Pressure Threshold Register (08H)…………………………………………………….. .……….……….…17
6.10 Flow Control Threshold Register ( 09H )…………………………………………………….……….……….…17
6.11 RX/TX Flow Control Register ( 0AH )……………………………………….…………….…..……………..…18
6.12 EEPROM & PHY Control Register ( 0BH )………………………………….…………….……………………18
6.13 EEPROM & PHY Address Register ( 0CH )…………………………………..………….………..……………18
6.14 EEPROM & PHY Data Register (0DH~0EH) ………………………………….……….………………………18
6.15 Wake Up Control Register ( 0FH )……………………………………………….…….…………..……………19
6.16 Physical Address Register ( 10H~15H )………………………………………….…….………….………….…19
6.17 Multicast Address Register ( 16H~1DH ) ……………………………………….…….…………...……………19
6.18 General purpose control Register
( 1EH )……………………………………….….……………….…………19
6.19 General purpose Register ( 1FH )………………………………………………….….…………………………20
6.20 TX SRAM Read Pointer Address Register (22H~23H)……………………………..……..……………………20
6.21 RX SRAM Write Pointer Address Register (24H~25H)……………………………..…………….……………20
6.22 Vendor ID Register (28H~29H)………………………………………………………..………………..………20
6.23 Product ID Register (2AH~2BH)………………………………………………………..………………………20
6.24Chip Revision Register (2CH)………………………………………………………….…….…….…………….20
6.25Transmit Control Register 2 ( 2DH ) ……………………………………………………..….…..………………20
6.26 Operation Test Control Register ( 2EH )…………………..………………………….……….….…..…………21
6.27 Special Mode Control Register ( 2FH )……………………...…………………………………….….…………21
6.28Early Transmit Control/Status Register ( 30H )…………………………………………………….……………22
6.29Check Sum Control Register ( 31H )……………………………………………………………….….…………22
6.30 Receive Check Sum Control Status Register ( 32H )…………………………………………….………………22
6.31 Memory Data Pre-Fetch Read Command without Address Increment (F0H)…………………….….….………23
6.32 Memory Data Read Command without Address Increment Register (F1H)………………..……….……..……23
6.33 Memory Data Read Command with Address Increment Register (F2H) ………………………….…….………23
6.34 Memory Data Read_address Register (F4H~F5H)………………………………………………………….……23
6.35 Memory Data Write Command without Address Increment Register (F6H)……………………………….……23
6.36 Memory data write command with address increment Register (F8H)…………….……………………….……23
6.37 Memory data write_address Register (FAH~FBH)………………………………….……………..……….……23
6.38 TX Packet Length Register (FCH~FDH)……………………………………………………………..…….……23
6.39 Interrupt Status Register (FEH)……………………………………………………………….…………….……24
6.40 Interrupt Mask Register (FFH)……………………………………………………….……….…………….……24
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
3
ETC [ ETC ]
