RTL8211C & RTL8211CL
Datasheet
List of Figures
FIGURE 1. RTL8211C PIN ASSIGNMENTS (64-PIN QFN)...............................................................................................................3
FIGURE 2. RTL8211CL PIN ASSIGNMENTS (48-PIN LQFP) ..........................................................................................................4
FIGURE 3. LED AND PHY ADDRESS CONFIGURATION ................................................................................................................11
FIGURE 4. TYPICAL MDC/MDIO READ TIMING..........................................................................................................................12
FIGURE 5. TYPICAL MDC/MDIO WRITE TIMING........................................................................................................................13
FIGURE 6. SWITCHING REGULATOR APPLICATION.......................................................................................................................34
FIGURE 7. INPUT VOLTAGE OVERSHOOT <4V (GOOD)................................................................................................................36
FIGURE 8. INPUT VOLTAGE OVERSHOOT >4V (BAD)...................................................................................................................36
FIGURE 9. CERAMIC 22µF 1210(X5R) (GOOD)............................................................................................................................37
FIGURE 10. CERAMIC 22µF 0805(Y5V) (BAD)..............................................................................................................................37
FIGURE 11. ELECTROLYTIC 100µF (RIPPLE TOO HIGH).................................................................................................................38
FIGURE 12. 4R7GTSD32 (GOOD).................................................................................................................................................39
FIGURE 13. 1µH BEAD (BAD)........................................................................................................................................................39
FIGURE 14. 64-PIN TYPICAL SWITCHING REGULATOR PCB LAYOUT (TOP LAYER)......................................................................40
FIGURE 15. 64-PIN TYPICAL SWITCHING REGULATOR PCB LAYOUT (BOTTOM LAYER) ..............................................................40
FIGURE 16. SWITCHING REGULATOR EFFICIENCY MEASUREMENT CHECKPOINT ..........................................................................41
FIGURE 17. POWER SEQUENCE......................................................................................................................................................42
FIGURE 18. APPLICATION DIAGRAM .............................................................................................................................................42
FIGURE 19. MDC/MDIO MANAGEMENT TIMING PARAMETERS ...................................................................................................44
FIGURE 20. RGMII TIMING MODES ..............................................................................................................................................46
Integrated 10/100/1000 Gigabit Ethernet Transceiver
vi
Track ID: JATR-1076-21 Rev. 1.3
ETC [ ETC ]
