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PIC16F877T-20PQ 参数 Datasheet PDF下载

PIC16F877T-20PQ图片预览
型号: PIC16F877T-20PQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器\n [8-Bit Microcontroller ]
分类和应用: 微控制器
文件页数/大小: 200 页 / 3338 K
品牌: ETC [ ETC ]
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PIC16F87X  
( PIE1<4>). Flag bit TXIF will be set, regardless of the  
state of enable bit TXIE and cannot be cleared in soft-  
ware. It will reset only when new data is loaded into the  
TXREG register. While flag bit TXIF indicates the status  
of the TXREG register, another bit TRMT (TXSTA<1>)  
shows the status of the TSR register. Status bit TRMT  
is a read only bit, which is set when the TSR register is  
empty. No interrupt logic is tied to this bit, so the user  
has to poll this bit in order to determine if the TSR reg-  
ister is empty.  
10.2  
USART Asynchronous Mode  
In this mode, the USART uses standard non-return-to-  
zero (NRZ) format (one start bit, eight or nine data bits,  
and one stop bit). The most common data format is 8  
bits. An on-chip, dedicated, 8-bit baud rate generator  
can be used to derive standard baud rate frequencies  
from the oscillator. The USART transmits and receives  
the LSb first. The USART’s transmitter and receiver are  
functionally independent, but use the same data format  
and baud rate. The baud rate generator produces a  
clock either x16 or x64 of the bit shift rate, depending  
on bit BRGH (TXSTA<2>). Parity is not supported by  
the hardware, but can be implemented in software (and  
stored as the ninth data bit). Asynchronous mode is  
stopped during SLEEP.  
Note 1: The TSR register is not mapped in data  
memory, so it is not available to the user.  
2: Flag bit TXIF is set when enable bit TXEN  
is set. TXIF is cleared by loading TXREG.  
Transmission is enabled by setting enable bit TXEN  
(TXSTA<5>). The actual transmission will not occur  
until the TXREG register has been loaded with data  
and the baud rate generator (BRG) has produced a  
shift clock (Figure 10-2). The transmission can also be  
started by first loading the TXREG register and then  
setting enable bit TXEN. Normally, when transmission  
is first started, the TSR register is empty. At that point,  
transfer to the TXREG register will result in an immedi-  
ate transfer to TSR, resulting in an empty TXREG. A  
back-to-back transfer is thus possible (Figure 10-3).  
Clearing enable bit TXEN during a transmission will  
cause the transmission to be aborted and will reset the  
transmitter. As a result, the RC6/TX/CK pin will revert  
to hi-impedance.  
Asynchronous mode is selected by clearing bit SYNC  
(TXSTA<4>).  
The USART Asynchronous module consists of the fol-  
lowing important elements:  
• Baud Rate Generator  
• Sampling Circuit  
• Asynchronous Transmitter  
• Asynchronous Receiver  
10.2.1 USART ASYNCHRONOUS TRANSMITTER  
The USART transmitter block diagram is shown in  
Figure 10-1. The heart of the transmitter is the transmit  
(serial) shift register (TSR). The shift register obtains its  
data from the read/write transmit buffer, TXREG. The  
TXREG register is loaded with data in software. The  
TSR register is not loaded until the STOP bit has been  
transmitted from the previous load. As soon as the  
STOP bit is transmitted, the TSR is loaded with new  
data from the TXREG register (if available). Once the  
TXREG register transfers the data to the TSR register  
(occurs in one TCY), the TXREG register is empty and  
flag bit TXIF (PIR1<4>) is set. This interrupt can be  
enabled/disabled by setting/clearing enable bit TXIE  
In order to select 9-bit transmission, transmit bit TX9  
(TXSTA<6>) should be set and the ninth bit should be  
written to TX9D (TXSTA<0>). The ninth bit must be  
written before writing the 8-bit data to the TXREG reg-  
ister. This is because a data write to the TXREG regis-  
ter can result in an immediate transfer of the data to the  
TSR register (if the TSR is empty). In such a case, an  
incorrect ninth data bit may be loaded in the TSR  
register.  
FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM  
Data Bus  
TXREG register  
TXIF  
TXIE  
8
MSb  
(8)  
LSb  
0
Pin Buffer  
and Control  
TSR register  
RC6/TX/CK pin  
Interrupt  
TXEN  
Baud Rate CLK  
SPBRG  
TRMT  
SPEN  
TX9  
TX9D  
Baud Rate Generator  
1999 Microchip Technology Inc.  
DS30292B-page 99  
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