PIC16F87X
4.8
Protection Against Spurious Write
4.9
Operation during Code Protect
4.8.1
EEPROM DATA MEMORY
Each reprogrammable memory block has its own code
protect mechanism. External Read and Write opera-
tions are disabled if either of these mechanisms are
enabled.
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
4.9.1
DATA EEPROM MEMORY
The microcontroller itself can both read and write to the
internal Data EEPROM, regardless of the state of the
code protect configuration bit.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
4.9.2
PROGRAM FLASH MEMORY
4.8.2
PROGRAM FLASH MEMORY
The microcontroller can read and execute instructions
out of the internal FLASH program memory, regardless
of the state of the code protect configuration bits. How-
ever the WRT configuration bit and the code protect bits
have different effects on writing to program memory.
Table 4-1 shows the various configurations and status
of reads and writes. To erase the WRT or code protec-
tion bits in the configuration word requires that the
device be fully erased.
To protect against spurious writes to FLASH program
memory, the WRT bit in the configuration word may be
programmed to ‘0’ to prevent writes. The write initiate
sequence must also be followed. WRT and the config-
uration word cannot be programmed by user code, only
through the use of an external programmer.
TABLE 4-1:
READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
Configuration Bits
Internal
Read
Internal
Write
Memory Location
ICSP Read ICSP Write
CP1
CP0
WRT
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
x
0
0
1
1
0
0
1
1
0
1
All program memory
Unprotected areas
Protected areas
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
No
No
No
Yes
No
No
Yes
No
Yes
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Unprotected areas
Protected areas
Yes
No
Unprotected areas
Protected areas
Yes
No
Unprotected areas
Protected areas
Yes
No
All program memory
All program memory
Yes
Yes
TABLE 4-2:
REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
10Bh, 18Bh
10Dh
10Fh
10Ch
10Eh
18Ch
18Dh
8Dh
EEADR
EEPROM address register
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
x--- x000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
x--- u000
EEADRH
—
—
—
EEPROM address high
EEDATA EEPROM data resister
EEDATH
EECON1
—
—
—
EEPROM data resister high
WRERR
EEPGD
—
—
WREN
WR
RD
EECON2 EEPROM control resister2 (not a physical resister)
PIE2
PIR2
—
—
(1)
(1)
—
—
EEIE
EEIF
BCLIE
BCLIF
—
—
—
—
CCP2IE
CCP2IF
-r-0 0--0
-r-0 0--0
-r-0 0--0
-r-0 0--0
0Dh
Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented read as ’0’. Shaded cells are not used during FLASH/
EEPROM access.
Note 1: These bits are reserved; always maintain these bits clear.
DS30292B-page 46
1999 Microchip Technology Inc.
ETC [ ETC ]
