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PIC16F877T-20PQ 参数 Datasheet PDF下载

PIC16F877T-20PQ图片预览
型号: PIC16F877T-20PQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器\n [8-Bit Microcontroller ]
分类和应用: 微控制器
文件页数/大小: 200 页 / 3338 K
品牌: ETC [ ETC ]
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PIC16F87X  
Counter mode is selected by setting bit T0CS  
(OPTION_REG<5>). In counter mode, Timer0 will  
increment either on every rising or falling edge of pin  
RA4/T0CKI. The incrementing edge is determined by  
the Timer0 Source Edge Select bit T0SE  
(OPTION_REG<4>). Clearing bit T0SE selects the ris-  
ing edge. Restrictions on the external clock input are  
discussed in detail in Section 5.2.  
5.0  
TIMER0 MODULE  
The Timer0 module timer/counter has the following fea-  
tures:  
• 8-bit timer/counter  
• Readable and writable  
• 8-bit software programmable prescaler  
• Internal or external clock select  
• Interrupt on overflow from FFh to 00h  
• Edge select for external clock  
The prescaler is mutually exclusively shared between  
the Timer0 module and the watchdog timer. The pres-  
caler is not readable or writable. Section 5.3 details the  
operation of the prescaler.  
Figure 5-1 is a block diagram of the Timer0 module and  
the prescaler shared with the WDT.  
5.1  
Timer0 Interrupt  
Additional information on the Timer0 module is available  
in the PICmicro™ Mid-Range MCU Family Reference  
Manual (DS33023).  
The TMR0 interrupt is generated when the TMR0 reg-  
ister overflows from FFh to 00h. This overflow sets bit  
T0IF (INTCON<2>). The interrupt can be masked by  
clearing bit T0IE (INTCON<5>). Bit T0IF must be  
cleared in software by the Timer0 module interrupt ser-  
vice routine before re-enabling this interrupt. The  
TMR0 interrupt cannot awaken the processor from  
SLEEP since the timer is shut off during SLEEP.  
Timer mode is selected by clearing bit T0CS  
(OPTION_REG<5>). In timer mode, the Timer0 mod-  
ule will increment every instruction cycle (without pres-  
caler). If the TMR0 register is written, the increment is  
inhibited for the following two instruction cycles. The  
user can work around this by writing an adjusted value  
to the TMR0 register.  
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER  
Data Bus  
8
CLKOUT (= FOSC/4)  
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI  
Pin  
SYNC  
2
Cycles  
TMR0 reg  
T0SE  
T0CS  
Set Flag Bit T0IF  
on Overflow  
PSA  
PRESCALER  
0
1
8-bit Prescaler  
M
U
X
Watchdog  
Timer  
8
8 - to - 1MUX  
PS2:PS0  
PSA  
1
0
WDT Enable bit  
M U X  
PSA  
WDT  
Time-out  
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).  
1999 Microchip Technology Inc.  
DS30292B-page 47  
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