PIC16F87X
FIGURE 15-20: A/D CONVERSION TIMING
BSF ADCON0, GO
(T
OSC
/2)
(1)
Q4
130
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLING STOPPED
132
9
8
7
...
...
2
1
131
1 T
CY
0
NEW_DATA
OLD_DATA
DONE
SAMPLE
Note 1:
If the A/D clock source is selected as RC, a time of T
CY
is added before the A/D clock starts. This allows the
SLEEP
instruction to be executed.
TABLE 15-13: A/D CONVERSION REQUIREMENTS
Param
No.
130
Sym Characteristic
T
AD
A/D clock period
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
131
132
T
CNV
Conversion time (not including S/H time)
(Note 1)
T
ACQ
Acquisition time
Note 2
10*
Min
1.6
3.0
2.0
3.0
Typ†
—
—
4.0
6.0
—
40
—
Max
—
—
6.0
9.0
12
—
—
Units
µs
µs
µs
µs
T
AD
µs
µs
The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on C
HOLD
).
If the A/D clock source is
selected as RC, a time of T
CY
is
added before the A/D clock
starts. This allows the
SLEEP
instruction to be executed.
Conditions
T
OSC
based, V
REF
≥
3.0V
T
OSC
based, V
REF
≥
2.0V
A/D RC Mode
A/D RC Mode
134
T
GO
Q4 to A/D clock start
—
T
OSC
/2 §
—
—
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
Note 1:
ADRES register may be read on the following T
CY
cycle.
2:
See Section 11.1 for min conditions.
*
†
©
1999 Microchip Technology Inc.
DS30292B-page 171
ETC [ ETC ]
