PIC16F87X
FIGURE 15-17: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-9: I2C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4.0
—
—
µs
µs
Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
0.6
Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
—
101
TLOW
Clock low time
100 kHz mode
4.7
µs
µs
Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
1.3
—
Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
—
102
103
TR
TF
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
90
91
TSU:STA START condition
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for repeated
START condition
setup time
THD:STA START condition hold 100 kHz mode
—
After this period the first clock
pulse is generated
time
400 kHz mode
100 kHz mode
400 kHz mode
—
106
107
92
THD:DAT Data input hold time
—
0
0.9
—
TSU:DAT Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
Note 2
—
TSU:STO STOP condition setup 100 kHz mode
—
time
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
109
110
TAA
Output valid from
clock
3500
—
Note 1
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast-mode (400 kHz) I C-bus device can be used in a standard-mode (100 kHz) I C-bus system, but the requirement tsu;
DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
2
TR max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I C bus specification) before the SCL line is
released.
DS30292B-page 168
1999 Microchip Technology Inc.
ETC [ ETC ]
