PIC16F87X
FIGURE 15-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 15-4 for load conditions.
FIGURE 15-8: BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40°C to +85°C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms VDD = 5V, -40°C to +85°C
32
Tost
Oscillation Start-up Timer Period
Power up Timer Period
—
28
—
1024 TOSC
—
132
2.1
—
TOSC = OSC1 period
33*
34
Tpwrt
TIOZ
72
—
ms VDD = 5V, -40°C to +85°C
µs
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
35
TBOR
Brown-out Reset pulse width
100
—
—
µs
VDD ≤ VBOR (D005)
Legend:
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
1999 Microchip Technology Inc.
DS30292B-page 161
ETC [ ETC ]
